Abstract: A system including at least one computation node including a memory, a processor reading/writing data in a work area of the memory and a DMA controller including a receiver receiving data from outside and writing it in a sharing area of the memory or a transmitter reading data in said sharing area and transmitting it outside. A write and read request mechanism is provided in order to cause, upon request of the processor, a data transfer, by the DMA controller, between the sharing area and the work area. The DMA controller includes an additional transmitting/receiving device designed for exchanging data between outside and the work area, without passing through the sharing area.

Abstract: There is disclosed a bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a first bus device interface comprising: a) a first incoming request bus for receiving request packets from a first one of the plurality of bus devices; b) a first outgoing request bus for transmitting request packets to the first bus device; c) a first incoming data bus for receiving data packets from the first bus device; and d) a first outgoing data bus for transmitting data packets to the first bus device; and 2) a second bus device interface comprising: a) a second incoming request bus for receiving request packets from a second one of the plurality of bus devices; b) a second outgoing request bus for transmitting request packets to the second bus device; c) a second incoming data bus for receiving data packets from the second bus device; and d) a second outgoing data bus for transmitting data packets to the second bus device.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: The present invention provides a data processing apparatus and method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units for accessing a bus in order to initiate processing requests, and a test controller for testing logic units of the data processing apparatus. Further, an arbiter is provided for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller. In a normal test mode, the test controller has a higher priority than any of the master logic units to be tested.

Abstract: This invention is to record data and skip an ECC block containing a defective sector when the defective sector is detected in an optical disk in which data is recorded in an ECC block unit constructed by 16 sectors and record a physical block number obtained by adding an amount of 16 sectors for each skipping into a reserve field of each sector of a next ECC block. Thus, continuous data such as moving pictures can be recorded in the ECC block unit, an ECC block containing the defective sector can be detected later in a case wherein the power supply is turned OFF by mistake or power failure in the course of recording when the recording process is effected while skipping an ECC block containing a defective sector, and data recorded up to the interruption can be reproduced without being influenced by the defective sector.

Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.