Abstract: Propositional reasoning is performed on a massively parallel processor, with sets of element value combinations being handled by separate processing units. A host processor operates as a problem solver generating requests for propositional reasoning, and also operates as an interface between the problem solver and the parallel processor. In response to a request that includes a formula, the interface provides one or more formulas such as justifications and class restrictions. The interface provides instructions to the parallel processor based on each of these formulas. The instruction based on each formula are provided so that the set of element value combinations handled by each processing unit is not divided or forked into two subsets until necessary. If possible, forking is avoided by forcing the value of an element to the only value consistent with the current formula.

Abstract: A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.

Abstract: A control system using a plurality of microcomputers prevents data transfer error by allowing execution of control programs by the respective microcomputers only after all the microcomputers have been initialized. The control system may be used for controlling, for example, a copying machine and a sorter.