Patents Examined by Paulina Lintsai
  • Patent number: 5485582
    Abstract: At data transfer, a processor sends an address to an address bus and sends a data to a data bus. In a transfer control unit, a comparator compares an outside address signal inputted via the address bus with an inside address signal generated in an address generating part. When the signals coincide with each other, the comparator outputs a coincidence signal. Receiving the coincidence signal, a control part sends a write signal to a buffer and a data on the data bus is stored in the buffer. The address generating part proceeds to a next address according to the write signal. The data in the buffer is sent outside from a port thereafter. Thus, a program for high-speed data transfer is easily programmed with an ordinary code of a processor for general purpose.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: January 16, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Ichiro Okabayashi
  • Patent number: 5469544
    Abstract: A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: November 21, 1995
    Assignee: Intel Corporation
    Inventors: Deepak J. Aatresh, Tosaku Nakanishi, Gregory S. Mathews
  • Patent number: 5434994
    Abstract: A system and method for maintaining data coherency in a system in which data is replicated on two or more servers. Each server is able to update the data replica present on the server. Updates are logged for each server. Reconciliation of server data replicas is aggressively initiated upon the occurrence of predefined events. These events include arrival at a scheduled time, a request for data by a client system, server and network failure recovery. Reconciliation is managed by a coordinator server selected to ensure that at most one coordinator server per network partition is selected. Logged updates are merged and transmitted to each server containing a data replica. The logged updates are applied unless a conflict is detected. Conflicts are collected and distributed for resolution. Reconciliation is managed between servers without regard to operating system or physical file system type.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: July 18, 1995
    Assignee: International Business Machines Corporation
    Inventors: Amal A. Shaheen, Krishna K. Yellepeddy