Abstract: A digital clock frequency multiplication and data serialization circuit for converting Q parallel data bits into a serial data stream is provided. A clock phase generator is coupled to receive the clock signal of the Q parallel data bits and output in response thereto Q synchronous clocks each of different phase. Logic circuitry is coupled to simultaneously receive the Q synchronous clocks and the Q parallel data bits. The Q synchronous clocks are used by the logic to gate a respective one of the Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream. Circuits are provided for simultaneous frequency multiplication and return-to-zero data serialization and simultaneous frequency multiplication and nonreturn-to-zero data serialization. Further, digital clock frequency multiplication and synchronization circuits for converting a low frequency signal to a high frequency signal are described.

Abstract: A parallel analog-to-digital converter having comparators in a sequence with two sets of logic gates having inputs electrically connected to selected primary and complementary outputs of the comparators.

Abstract: An AC solid state switch includes an inverse parallel connection of a pair of silicon controlled rectifiers. A circuit branch which includes the series connection of the main conducting paths of a pair of field effect transistors is electrically connected in parallel with the inverse parallel arrangement of silicon controlled rectifiers. Gate power sources provide continuous gate drive signals to the silicon controlled rectifiers and field effect transistors. By including the field effect transistors, voltage transients across the switch are reduced in high frequency AC power systems.