Abstract: The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1. Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1.