Abstract: The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating the mounting of a circuit component, such as a decoupling capacitor, fabricated separately from the substrate. The substrate for a semiconductor device, on which the circuit component, such as a decoupling capacitor, can be mounted, is counterbored from the mounting surface side thereof, and a component mounting hole where a connection terminal, which will be electrically connected to the circuit component, is exposed in the inner bottom face is made by counterboring. The circuit component is mounted and electrically connected to the connection terminal, and a semiconductor element is mounted on the substrate by flip-chip connection.

Abstract: The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from a radiative recombination of electron and holes on semiconducting single walled carbon nanotubes (SWNTs-LED). We will also show how it is possible to implement these SWNTs-LED in order to build up a laser source based on the emission properties of SWNTs. A description of the manufacturing process of such devices is also given.

Abstract: A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-standard, reversed option RO for the layout of the bonding-pads. The double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. One of the chips has its wire-bonding-pads electrically reversed such that the wire-bonding pads on both chips are located near each other to accommodate wire-bonding to a common bonding finger of a lead frame. A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed pattern for the reversible wire-bonding-pads.

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Abstract: A semiconductor package configuration is proposed for use to pack an semiconductor chip of an optically-sensitive type, such as an image-sensor chip or an ultraviolet-sensitive EP-ROM chip. This type of semiconductor chips are encapsulated in an encapsulation body having a centrally-hollowed portion whose opening is covered with a lid. This semiconductor package configuration is characterized in the use of a lead frame having a die-pad portion formed with a shouldered portion at the edge thereof and having a lead portion formed with a recessed portion at the point where the inner wall of the centrally-hollowed portion of the encapsulation body is located. The shoulder portion and the recessed portion are used to help prevent the flash of resin on lead frame during the molding process to form the encapsulation body in the manufacture of the semiconductor package configuration.

Abstract: A tape carrier is constituted comprising land 12 for solder ball, formed in a predetermined pattern on insulating film 7 having device hole 10 formed in the middle, leads 9 to be connected to a semiconductor chip, plating power-feeding lead 13 having one end connected to lead 9 and formed on insulating film 7, and easily-broken part 19 provided in the middle of the power-feeding leads. A semiconductor device is constituted wherein tape carrier 2 is provided with plating power-feeding lead 13 formed on insulating film 7, one end of which is drawn out of insulating film 7, the other end being connected to leads 9, and plating power-feeding lead 13 is disconnected from the leads when semiconductor chip 1 is installed. Thus, a tape carrier for BGA which is manufactured easily, capable of achieving higher density of wiring in the wiring pattern, improved in water-resistance and reliability, and a semiconductor device using the same are provided.

Abstract: External connection terminals (25) are disposed on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element (20) such as an image sensor, a solid state imaging device, etc. The external connection terminals (25) are connected electrically to an integrated circuit (21) of the optical element (20) via wirings (23). The wirings (23) are connected electrically to electrical measuring electrodes (23T) in the course of wafer process, but the electrical measuring electrodes (23T) are disconnected from the wirings (23) after the electrical measurement has been completed. The electrical measuring electrodes (23T) are formed on dicing lines and then removed at the same time when dicing process is executed. The external connection terminals (25) are connected to the wirings (23) from which the electrical measuring electrodes (23T) are disconnected.