Abstract: In an address generating device wherein addresses are generated by an address computation part in response to data and control signals read out of an instruction memory and are provided to a memory under test, a command control bit for storing a command control signal is provided in the instruction memory and a command register is provided for storing a command read out of a data area of the instruction memory. The output from the address computation part and the output from the command register are input into a first multiplexer, which selects either one of the two inputs in response to a command control signal read out of the command control bit. The output from the first multiplexer is applied to a descrambler, wherein it is translated to a physical address. A second multiplexer is provided for selecting either one of the outputs from the descrambler and the first multiplexer in such an instance.

Abstract: A boundary scan test circuit that includes Y scan flip-flops serially connected in a sequence from a first scan flip-flop to a Y.sup.th scan flip-flop and clocked with a system clock signal, and circuitry for providing scan input data to the first scan flip-flop synchronously with a test clock signal and for receiving scan output data from the Y.sup.th scan flip-flop synchronously with the test clock signal, wherein the test clock signal and the system clock signal have a test clock period to system clock period ratio that is equal to any fixed integer ratio M.

Abstract: A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention.

Abstract: In a watchdog timer circuit for a system having a central processing unit and a storage unit, a watchdog timer is provided, which counts up to a predetermined counter value and generates an alarm signal for the central processing unit when the predetermined counter value has been reached. A reset unit is connected to the watchdog timer to periodically reset the watchdog timer in response to a first reset signal generated by the central processing unit, so that the watchdog timer is reset to an initial state. A data comparing unit is coupled to the storage unit to detect whether or not the storage unit is accessible and output a second reset signal to the watchdog timer each time it is detected that the storage unit is accessible.

Abstract: A system and method for detecting fault conditions within a vehicle recording device are disclosed herein. The fault detection technique may be implemented in a vehicle in which are incorporated one or more vehicle sensors for monitoring one or more operational parameters of the vehicle. A recording device disposed within the vehicle is used to collect vehicle operation data produced by the one or more vehicle sensors.The fault detection technique of the invention contemplates storing a current time value at regular intervals during periods in which the recording device is provided with a source of main power. Time differences are determined between consecutive ones of the stored time values, and the time differences compared to a predetermined maximum value. A power loss fault condition is registered when at least one of the time differences exceeds the predetermined maximum value.

Abstract: A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

Abstract: A set/reset scan flip-flop circuit normally inhibits set/reset operations in the scan mode, but allows a set/reset occurring in the last scan cycle to pass through. The circuit includes a multiplexer that receives a data signal and a scan signal. The scan signal is selected as the multiplexer output when Test Enable, which serves as the multiplexer select signal, is active. The Test Enable signal and the set/reset signal are provided as inputs to an OR gate such that, if Test Enable is active high, then the OR gate output is also high. The OR gate output is connected to the set/reset pin of a flip-flop. The multiplexer output drives the data input of the flip-flop. Therefore, assuming that the set/reset signal is active low, when in the scan mode, i.e., Test Enable is active high, the OR gate blocks the set/reset signal from the flip-flop. However, if set/rest goes active low in the last scan cycle, then the low-going Test Enable allows the set/rest to pass through.

Abstract: A measurement of the distinctness of Finite State Machine (FSM) (33) model state transitions can expedite identification of Unique Input/Output Sequences (UIO) (63). The Input/Output (I/O) sequences associated with FSM model (33) state transitions are compared. Each different I/O sequence is replaced by a different label so that transitions with the same I/O sequence have the same label and transitions with different I/O sequences have different labels. A transformation of the count of the number of times that each label is found in the FSM model, or a subset thereof, is determined, and assigned to each corresponding transition as a Distinctness Measurement (58). This Distinctness Measurement can be used to expedite a depth-first search for Unique Input/Output Sequences (63).

Abstract: A data output encoder capable of having its state of retaining internal error information and self-diagnostic information reset without recourse to removing power or furnishing a dedicated signal line. A reset pulse generator monitors the changing status of an externally provided output request signal. When the signal status reaches a predetermined pattern, the reset pulse generator generates reset pulses that cause an RS flip-flop circuit to reset the state in which the internal error information and self-diagnostic information are retained.

Abstract: A system and method for providing debugging of a data processing system having a plurality of resources, a keyboard and a multitasking operating system including a plurality of protection domains and a keyboard device driver which executes in a protection domain having maximum access privileges to system resources. A debugging module in the keyboard device driver is provided. Responsive to user selection through a predetermined key stoke sequence, the debugging module may be invoked. Utilizing the debugging module, various system registers and memory locations are accessed and the contents placed in the keyboard input buffer for display on a computer monitor.

Abstract: A testing unit allows an operator to select and test communication links of a communication system between an intermediate station and remote stations. Each remote station contains another communication link for establishing a second communication system between the intermediate station and the remote stations. The testing unit contains a first communication link for receiving and transmitting signals generated from a computer. This first communication link is part of the second communication system. The testing unit also includes a control unit which is connected to the first communication link for receiving and transmitting signals therefrom, and a second communication link which is connected to the control unit for receiving and transmitting signals therefrom. The second communication link is part of the second communication system so that communication can be established between the computer and the remote stations via the intermediate station by means of the second communication system.

Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data.

Abstract: An apparatus and method for increasing the mean time between failure for computer systems is disclosed. A single spare line can be used to replace any of several signal lines. Using 2:1 multiplexers, defective signal lines can easily be switched to a nonoperative state and the remaining signal lines shifted to provide for replacement of the defective line without significant path length increase or signal time delay. The invention is applicable to signal paths of different varieties, including electrical, electro-optical and fluidic.

Abstract: An information processing system includes a simplex system and a duplex system in which at least two data transmitting systems are provided each capable of being an act system or a standby system. Each data transmitting system has a data acquiring unit. The simplex system includes a controller for controlling a selector to switch between the systems. When in a standby condition, the data acquiring unit of the respective data transmitting system in the duplex system issues an access request signal to a switching signal generating unit provided in the controller of the simplex system to request that the output of the selector be switched from the act system to the standby system in the duplex system. Upon receipt of the access request signal from the data acquiring unit in the standby system, the switching signal generating unit switches the selector to the standby system.

Abstract: When a test access port (TAP) controller based on the U.S. standard IEEE 1149.1 is used, a gate is provided for controlling the signal output of its shift register so as to turn high when it is in the normal condition to control the selector signal so that, during the normal operation, the input terminal is set disable at the selector circuit within the boundary scan register cell. As a result, it can be completely prevented that the penetrating current, which can be induced when the input selector signal is on the intermediate level of potential, be induced within the selector circuit or DFF circuit within the boundary scan register.

Abstract: Input data symbols are written to a synchronization (sync) adder, which appends a pseudo randomly (PN) generated sync bit to generate a sync word. Sync words are sent to a receiver where synchronization is recovered. The receiver re-generates the same PN sequence that was generated at the transmitter. Synchronization recovery apparatus conceptually looks at each bit position to locate the appended PN sequence. When the sync bit position is found, the data stream is assembled into fixed length sync words and the data symbols of the sync words are written into a buffer at an address determined by the position of the sync bit in the PN sequence. Error rates in the data stream of sync words are measurable using a correlator network for reading the bit in the sync bit position of a sync word and for comparing that bit with its expected value in a reconstructed PN sequence to provide a difference value where the difference is a measure of the error rate in the data stream.

Abstract: In a shift correction decoder which processes d,k-constrained RLL data that is encoded in accordance with a shift correction code whose symbols in GF(p) comprise modulo p reductions of cumulative sums of successive run symbols of the RLL data (where p is an odd prime), additive errors (i.e., drop-out and drop-in errors) in the received RLL data are corrected by relying in part on information pertaining to the sequence of the polarities of successive 1-bits in the received RLL data. The polarity information is used to either insert missing 1-bits (due to drop-outs) or delete spurious 1-bits (due to drop-ins) and specify to the shift correction decoder the location of an additive error as an erasure. Synchronization slips are corrected by pre-multiplying the received codeword polynomial by a factor which reduces to two the number of errors created by a single synchronization slip. GF(p) is selected such that p.ltoreq.

Abstract: Circuitry for detecting and correcting errors in data words occurring in Reed-Solomon coded blocks contains a plurality of stages. One stage constructs syndromes in the data flowing through the blocks. Another stage detects erasures in the syndromes. Another stage applies a Euclid's algorithm withT.sub.s (x)={Q.sub.s-1 (x).multidot.T.sub.s-1 (x)}+T.sub.s-2 (x),R.sub.s (x)={Q.sub.s-1 (x).multidot.R.sub.s-1 (x)}+R.sub.s-2 (x),andI Q.sub.s-1 (x)=R.sub.s-2 (x)/R.sub.s-1 (x)wherein T.sub.s (x), R.sub.s (x), and Q.sub.s-1 (x) are polynomials representing the position of the error, its value, and a provisional value respectively, and R.sub.s (x) and T.sub.s (x) can be normalized with a minimal coefficient T.sub.s (0)=.delta. such that R(x)=R.sub.s (xi/.delta. and T(x)=T.sub.s (x)/.delta.. Another stage detects error positions X.sub.k and values Y.sub.k by conducting a Chien zero-root search in conjunction with ##EQU1## wherein T'(X.sub.k) is the first derivative of T at a place x.sub.k.

Abstract: To detect a delay fault along a signal path of interest (12) in a sequential digital circuit (10), a source flip-flop (14) and a destination flip-flop (16), proximate the beginning and end of the path, respectively, are designated in the circuit. Next, the signal path is activated to establish what logic values are necessary at the input of each of a set of combinational elements (18.sub.1 -18.sub.p) in the path to propagate a selected signal transition from the source flip-flop to the destination flip-flop. A first and second backward justification process is carried out to synthesize a first sequence to propagate a selected logic value from a primary circuit input to the source flip-flop to cause it to generate the selected signal transition to propagate to the destination flip-flop. A second backward justification process is carried out to synthesize a second vector sequence which serves to propagate the value latched in the destination flip-flop to a primary output.

Abstract: A cache coherency test exercises cache coherency logic exhaustively such that any cache coherency failures liable to occur will occur. The CPU(s) which caused the failure is automatically identified by performing an automatic CPU sort. In particular, cache coherency is tested by causing each processor in the system to perform a sequence of read and write accesses to main memory and to its own cache memory so as to cause substantially every possible sequence of cache coherency bus operations. Each processor tests consistency of data read by it with data written by it. As long as no processor detects an error, read and write accesses are continued for a predetermined period of time. When any processor detects an error, each CPU is disabled, one at a time, to see if the remaining CPUs can run the test successfully. If they do not, then every combination of two CPUs are disabled, then every combination of three, etc. In this manner, a maximum running set of CPUs is identified.