Abstract: A process for producing a solid image pickup device is demanded that can enhance a photoelectric conversion region by forming an overflow barrier layer at a deep position and can prevents generation of radiation due to the use of resist as a mask. Upon producing a solid image pickup device having a vertical overflow drain structure, ion implantation is conducted on an entire of a silicon substrate without using a resist mask, so as to form an overflow barrier layer. It is also possible that a trench is formed in a peripheral part of the silicon substrate to surround a pixel region and to separate the overflow barrier layer into the pixel region and an outer peripheral part, and an impurity diffusion layer having a conductive type different from that of the overflow barrier layer is formed on an inner surface of the trench.

Abstract: A method for attaching an integrated circuit die to a mounting structure, the method having the steps of: forming a mounting structure having a die pad and at least one spreader; applying an adhesive to the die pad and the at least one spreader of the mounting structure; and attaching the integrated circuit die to the adhesive, wherein the at least one spreader is between the die pad and the integrated circuit die. Also, an integrated circuit package having: a mounting structure having a die pad and at least one spreader; an adhesive adhered to the die pad and the at least one spreader of the mounting structure; and an integrated circuit die adhered to the adhesive, wherein the at least one spreader is between the die pad and the integrated circuit die. Finally, a mounting structure for an integrated circuit die, the mounting structure comprising: a die pad for supporting the integrated circuit die; and at least one spreader for supporting the integrated circuit die at a distance from the die pad.

Abstract: A dual damascene manufacturing process, which is applicable to a dual damascene structure, is described. The method includes forming sequentially a first organic dielectric layer with a low dielectric constant, a thermal diffusion layer and a second organic dielectric layer with a low dielectric constant on a substrate. A first mask layer with a trench line pattern and a second mask layer with a via opening pattern are then formed on the substrate, respectively. The second organic dielectric layer with a low dielectric constant and the thermal diffusion layer are etched using the second mask layer as a hard mask layer to transfer the via opening pattern onto the thermal diffusion layer, and the second mask layer is then removed. The first and the second organic dielectric layer with a low electric constant are removed by using the first mask layer and the thermal diffusion layer as hard mask layers to form a trench line and a via opening. After that, the dual damascene structure is completed.

Abstract: The present invention provides a method for forming a barrier layer, preferably a conductive barrier layer. According to the present invention, a barrier layer is formed from an organometallic precursor in the presence of an oxidant in a low temperature deposition technique using a platinum containing precursor. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

Abstract: The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.

Abstract: The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer.

Abstract: A method of forming an organic polymer insulator in a semiconductor device comprises the step of causing a thermal polymerization of at least one kind of monomers and oligomers supplied in vapor phase.

Abstract: A method for recycling a used silicon wafer on which ICs have been formed by IC fabrication equipment comprised of first grinding the wafer using a coarse grinding apparatus and then grinding the wafer suing a fine grinding apparatus. The coarse grinding apparatus and the fine grinding apparatus are identical to one another except for the nature of the respective grinding they perform. Deionized water is used during both grinding processes to reduce friction and to control dust. The used wafer is first mounted on a chuck of the coarse grinding apparatus that rotates at a first predetermined speed. A diamond wheel mounted on a grinding wheel holder of the coarse grinding apparatus rotates at a second predetermined speed that is faster than the first speed. The rotating wheel and the rotating wafer are brought into contact with one another and the wafer is ground until a predetermined amount of semiconductor material is removed from the face of the wafer.

Abstract: In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate.

Abstract: A method of manufacturing high-voltage MOS devices that uses trenches instead of field oxide layer as the isolating structure, and employs a vertical layout rather than a horizontal layout to lengthen the drift region for a given device area in a wafer. Therefore, this invention is capable of fabricating CMOS transistors in the sub-micron regime, and hence is able to increase the level of circuit integration for a given wafer. Furthermore, the present invention provides a method of manufacturing an assembly with different types of high-voltage MOS devices. By making minor adjustments in the height of the N.sup.- regions underneath the source/drain (N.sup.+) regions of different devices, an assembly of MOS devices each having a different voltage operating range can be obtained on an integrated circuit. Moreover, the minor adjustments can be achieved simply by etching the N.sup.- regions to different degrees.

Abstract: A vertical transistor semiconductor and method of making a vertical transistor is provided. The vertical transistor is particularly suited for use in a DRAM cell. The structure permits a DRAM cell to be fabricated with a comparatively low number of masking layers. Moreover, the vertical nature of the transistor allows a larger number of transistors per surface area compared to conventional techniques. The method and apparatus also utilizes a buried digit line. The digit line may include a portion that is a metal material that in a preferred embodiment is step-shaped sidewall of the digit line. The transistor is particular suited for use with a variety of DRAM capacitors.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.