Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

Abstract: An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, for each spreading code.

Abstract: Zipper is the time-synchronized frequency-division duplex implementation of discrete multi-tome (DMT) modulation. Two communicating Zipper modems transmit DMT symbols simultaneously with a common clock. When all transmitters are time synchronized, the near end cross-talk (NEXT) and near end echoes injected into the received signal are orthogonal to the desired signal. The present invention provides a telecommunications transmission system using zipper and having at least two VDSL systems. Each VDSL system comprises a pair of zipper modems communicating over a cable transmission path. The telecommunications transmission system handles zipper transmission transmitted over the common cable; at least partly mitigates NEXT; and permits transmissions in a first VDSL system which are asynchronous with transmissions in a second VDSL system.

Abstract: A tangent angle computation device and associated DQPSK decoder. The computation device uses an eight-bit divider and a four-quadrant technique for finding a quantized angular value from an incoming signal. The quantized angular value is subsequently used to decode the incoming signal.

Abstract: A testing system is provided with a pseudo random number generating circuit which generates a pseudo random number on the basis of a 125 MHz clock output from a 5-multiply circuit inside a clock recovery circuit, and an expected value generating/comparator circuit which collates a 125 Mbps recovered data output from the clock recovery circuit with an expected value data each 5 bits, and outputs the collation result as a 1-bit test output. The clock recovery circuit and the testing system are provided on the same LSI and are operated at a 125 MHz high frequency clock. However, the clock recovery circuit outputs a test output as recognized as a 25 MHz low speed data in the outside of LSI to the external elements.

Abstract: A decoding system to achieve rates higher than 33.6 kbps in the analog modem to digital modem direction. The decoding system modifies the standard Tomlinson Harashima Precoding algorithm to adapt it for use in PCM modems. Instead of an arithmetic modulo operation that is implemented in the transmitter, the invention defines a Discrete Modulo Operation that performs the function of limiting the amplitude of the transmitted signal.

Abstract: A subscriber unit receives a plurality of first spread spectrum signals. Each first spread spectrum signal has a first code. An impulse response of multipath components of each received first spread spectrum signal are analyzed to determine a first received component of that received first spread spectrum signal. In one embodiment, for each received first spread spectrum signal, a second spread spectrum signal having a second chip code time synchronized to the first received component of that received first spread spectrum signal is transmitted. In another embodiment, a code timing difference is determined between the first received components of the received first spread spectrum signals. The code timing difference is transmitted.

Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be acquired by searching for a first gated pilot signal, deriving timing information from the search for the first gated pilot signal, and searching for a second gated pilot signal using the timing information. This can be implemented in a variety of fashions including a receiver with a searcher configured to generate a bit sequence, a correlator configured to correlate a received signal with the bit sequence, and a processor configured to detect a first gated pilot signal as a function of the correlation, derive timing information from the first gated pilot signal, and detect a second gated pilot signal by using the timing information to control the bit sequence generated by the searcher. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A data communications receiver incorporating soft decision error correction decoding and a means to set the amplitude or threshold for quantized soft decisions in a near-optimum manner to a soft decision decoder. In one embodiment the means for setting the amplitude or threshold measures the soft decisions from a quantizer and marks data bits as weak or strong. The gain or threshold is automatically adjusted to achieve a desired fraction if each marking. The desired fraction is chosen as the value that optimizes performance of the soft decision decoder.

Abstract: In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract: A digital GMSK filter for use for frequency modulation of a carrier signal in a GMSK transmission system is described. The GMSK filter uses a large number of individual current sources, whose current values are individually weighted. The current sources are driven via a control logic module using a shift register with a thermometer code, such that this results in a total current with a Gaussian characteristic, which is converted across a resistor to a voltage and drives a voltage controlled oscillator (VCO). The filter provides exact implementation of the sample values, virtually without any quantization error, and requires only a small chip area for its implementation.

Abstract: Techniques for transmitting data from a transmitter unit to a receiver unit in a multiple-input multiple-output (MIMO) communication system. In one method, at the receiver unit, a number of signals are received via a number of receive antennas, with the received signal from each receive antenna comprising a combination of one or more signals transmitted from the transmitter unit. The received signals are processed to derive channel state information (CSI) indicative of characteristics of a number of transmission channels used for data transmission. The CSI is transmitted back to the transmitter unit. At the transmitter unit, the CSI from the receiver unit is received and data for transmission to the receiver unit is processed based on the received CSI.

Abstract: A tracking data receiver which can compensate for deterministic jitter is disclosed. The device utilizes a history of past data received to determine which of multiple samples taken within a bit period to utilize. Due to deterministic jitter that can occur in data signal communication, the delay of waveform development varies with the ratio of 0's to 1's transmitted prior to the bit period being observed. The present invention exploits the predictable nature of the deterministic jitter to decide which sample to choose.

Abstract: A demodulation system capable of configuring itself responsive to channel conditions. A plurality of detectors may be provided, one or more of which may be better able to handle a particular form of interference than one or more of the other detectors. The detectors estimate source bits from a common signal. One or more signal quality estimators receive the estimated bits for the detectors, and provide performance metrics for each of the detectors. A selector selects or continues the pre-selection of one of the detectors responsive to the performance metrics. A multiplexor outputs the estimated bits from the selected or pre-selected detector.

Abstract: An equalizing apparatus includes an equalizer which has a plurality of adjustable tap weights that equalizes a received signal based on values of the adjustable tap weights, a tap weight update calculation unit coupled to the equalizer and which determines tap weight updates for use in adjusting the tap weights during operation of the equalizer, an offset memory that stores one or more tap weight update offset values and a summer coupled to the tap weight update calculation unit and to the offset memory. The summer combines each of the tap weight updates with one of the tap weight update offset values to produce modified tap weight updates which, in turn, are provided to the equalizer to adjust the tap weights.

Abstract: When an antenna receives a signal, the signal is inputted to delayers through a frequency converter, A/D converters, quadrature demodulators, filters and simultaneously is inputted to a MUX. The receiving signal inputted to the MUX is transmitted to an interference canceler panel, and the interference canceler panel generates both an interference replica signal and a symbol replica signal. The interference canceler panel demodulates the receiving signal for a channel corresponding to the symbol replica signal using both the interference and symbol replica signals. The interference replica signal generated by the interference canceler panel is transmitted to a transmitting/receiving panel and is inputted to interference elimination units. The interference elimination units eliminates interference components by subtracting the interference replica signal from the receiving signal delayed by the delayers and transmits the signal to a baseband signal processing panel.

Abstract: A data demodulating technique for binary data defined by a pulse code modulated signal. The technique involves digitizing the data signal read by a magnetic head from the stripe of a magnetic card. The time interval between peaks in the digitized signal is determined to provide peak interval values. The peak interval values form the basis for determining the end of a character and also by a pattern matching technique against idealized data form the basis for determining the character itself.

Abstract: The invention relates to a reception method and a receiver to receive signals supplied from a radio path, and the signals include information and each signal which arrives at the receiver is delayed by a unique delay value. The receiver includes a filtering device and a distribution device to determine the strength of a part of a signal delayed by a certain propagation delay by several values of the propagation delay. The distribution device compares the delay differences of the received signals with each other and forms sums of the strengths of the signal parts determined by different values of the propagation delay. The distribution device selects values deviate at least by a predetermined delay difference whose sum of the strengths of the signal parts obtains the highest possible value. The receiver indicates the received information by using the signals selected above.