Abstract: An organic light-emitting diode (OLED) array substrate and an OLED display device are provided. The OLED array substrate includes a plurality of driving circuits of a plurality of sub-pixels using a mirror symmetrical structure, and a plurality of reset signal lines and a plurality of power signal lines extending along a same direction. By sharing each of the reset signal lines and each of a plurality of first vias, and sharing each of the power signal lines and each of a plurality of second vias, about half of lines of power signal lines, reset signal lines, and vias are saved. Therefore, room for increasing pixels per inch (PPI) is provided, facilitating realizing high PPI panel designs.

Abstract: A display substrate includes a base substrate; a plurality of light emitting blocks on the base substrate, a respective one of the plurality of light emitting blocks in a subpixel region; a unitary cathode layer electrically connected to the plurality of light emitting blocks, the unitary cathode layer extending substantially throughout a display area of the display substrate; an organic auxiliary cathode layer electrically connected to the unitary cathode layer, the organic auxiliary cathode layer including an organic conductive polymer material; and a metallic auxiliary cathode layer limited in a groove defined by the organic auxiliary cathode layer and in direct contact with the organic auxiliary cathode layer and in direct contact with the unitary cathode layer. The metallic auxiliary cathode layer is limited in an inter-subpixel region of the display substrate. The organic auxiliary cathode layer is at least partially in the inter-subpixel region of the display substrate.

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

Abstract: An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.

Abstract: The present application provides a Quantum Dot Light Emitting Diode (QDLED), comprising an anode, a p-type graphene layer, a hole injection layer, a quantum dot light-emitting layer and a cathode, the anode and the cathode is oppositely disposed, the quantum dot light-emitting layer is disposed between the anode and the cathode, the p-type graphene layer is disposed between the anode and the quantum dot light-emitting layer, and the hole transport layer is disposed between the p-type graphene layer and the quantum dot light-emitting layer, wherein the p-type graphene layer is made from p-type doped graphene, and the p-type doped graphene is at least one selected from a doped graphene via adsorption and a doped graphene via lattice.

Abstract: A double-sided organic light emitting diode (OLED) display panel is disclosed and includes a plurality of sub-pixels each of which has a top emission region and a bottom emission region. The top emission region has a first anode metal layer, a first OLED device layer, a first cathode metal layer, and an organic barrier layer. The bottom emission region has a second anode metal layer, a second OLED device layer, and a second cathode metal layer. The present invention can reduce an overall thickness of the double-sided OLED display panel.

Abstract: A display device is provided. The display device includes a first substrate, a first detection electrode on the first substrate, a first bank including an opening that exposes the first detection electrode, a photosensitive layer on the first detection electrode, a second detection electrode on the photosensitive layer, a first electrode on the second detection electrode, a second bank including an opening that exposes the first electrode, a light emitting layer on the first electrode, a second electrode on the light emitting layer, a first optical system between the second detection electrode and the first electrode, and a second optical system on the second electrode, wherein the first optical system and the second optical system overlap the photosensitive layer in a thickness direction of the display device.

Abstract: A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern.

Abstract: An optoelectronic component includes an optoelectronic semiconductor chip including a connection surface; a first potting body; and a second potting body, wherein the first potting body covers all lateral side surfaces and the top surface of the semiconductor chip, the first potting body has a bottom surface flush with the connection surface, the second potting body has a bottom surface flush with the bottom surface, the second potting body completely covers all side surfaces of the first potting body facing away from the semiconductor chip, a top surface of the second potting body on the opposite of the connection surface is convexly curved, the first and second potting bodies have a contour in a lateral plane that is not similar, and the optoelectronic semiconductor chip has exclusively on its connection surface exposed electrical contact surfaces via which the semiconductor chip is electrically connectable and operable.

Abstract: Provided is a TFT driving backplane including, in top-to-bottom order, a sub-data line, a first insulating layer, a top capacitor plate, a second insulating layer and a bottom capacitor plate. In one side of the top capacitor plate is provided a notch filled upward by the first insulating layer provided with a first via extending vertically downward to the bottom capacitor plate. By moving the position where the sub-data line and the bottom capacitor plate are connected away from the top capacitor plate, holing is not required to be performed at the center of the capacitor and two-step opening alignment is avoided. Consequently, the requirement for alignment precision in photolithography is less critical, and the deviation due to two-step opening alignment is prevented. Meanwhile, by designing the margin and the one-way deviation, the short circuit in the capacitor can be avoided, and the effective capacitive area can be increased.

Abstract: A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode.

Abstract: A method of manufacturing an electroluminescent device includes providing a substrate including a first pixel and a second pixel configured to emit different colors; forming a first light-emitting layer and a first protecting layer over the substrate through a first opening of a first sacrificial layer; forming a second light-emitting layer and a second protecting layer over the substrate through a second opening of a second sacrificial layer; removing the first sacrificial layer together with the second sacrificial layer; and removing the first protecting layer from the first light-emitting layer, and the second protecting layer from the second light-emitting layer.

Abstract: The present invention provides a display including: a pixel definition layer having a plurality of strip-shaped openings arranged in at least two columns or at least two rows parallel to each other; and a plurality of sub-pixels, wherein at least two adjacent sub-pixels are disposed in each of the strip-shaped openings.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: A display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulation layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulation layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulation layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulation layer, the capacitor electrode overlapping the first gate electrode, wherein a permittivity of the first gate insulation layer is greater than a permittivity of the buffer layer.

Abstract: A semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first memory cell and a second memory cell. The first memory cell includes a first transistor. The second memory cell includes a second transistor. The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The first transistor includes a first metal oxide. The second transistor includes a second metal oxide. Each of the first metal oxide and the second metal oxide includes a channel formation region. Each of the first metal oxide and the second metal oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. The atomic ratio of the element M to In in the second metal oxide is greater than that in the first metal oxide.

Abstract: A display panel and a method of fabricating the same are provided. The display panel has an array substrate having a substrate, a thin film transistor unit and a storage capacitor disposed on the substrate; a light emitting device layer disposed on the array substrate. An orthographic projection of the storage capacitor projected on the light emitting device layer is located within the light emitting device layer.

Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.

Abstract: The present invention discloses an array substrate and a display panel. The array substrate comprises a substrate, an anode layer disposed on the substrate, and a first retaining wall disposed on the anode layer and around the display area. The anode layer is provided with a first stress buffer area corresponding to the first retaining wall, and the first stress buffer area is provided with a first via structure passing through the anode layer.

Abstract: A display panel may include the following elements: a substrate including an opening area, a display area surrounding the opening area, and a first non-display area between the opening area and the display area; a data line positioned at a first side relative to the opening area; a first scan line; a second scan line; a first pixel connected to the data line and the first scan line; a second pixel connected to the data line and the second scan line; a first emission control line connected to the first pixel; a connecting section positioned on the first non-display area; a second emission control line connected to the second pixel and connected through the connecting section to the first emission control line; and an emission control driver configured to simultaneously provide emission control signals to the first emission control line and the second emission control line.