Patents Examined by Pierr-Michel Bataille
  • Patent number: 6918010
    Abstract: In prefetching cache lines from a main memory to a cache memory, an array of memory locations to be prefetched is determined and a base address indicating a highest address in the array is identified as well as a loop index used to point to the first address in the array. A prefetch index, which is the loop index plus a latency/transfer value, is used to prefetch memory locations as the array is processed. After a memory location is prefetched and initialized, the loop index and the prefetch index are incremented. The prefetch index is compared to a threshold value. If the prefetch index is less than the threshold value, then the next memory location in the array is prefetched and the prefetch index is again incremented and compared to the threshold value. If the prefetch index is equal to or greater than the threshold value, then the prefetch instruction is converted to a no operation instruction to prevent memory locations outside of the array from being prefetched during the processing of the array.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: July 12, 2005
    Assignee: Silicon Graphics, Inc.
    Inventor: Kenneth C. Yeager