Abstract: Decoding apparatus for decoding received adaptive differential pulse code modulation data signals which includes unit for quickly detecting errors in the data values in the form of unallocated values or values which are unlikely to occur. The apparatus is intended for use in cordless telephones to eliminate extraneous and disturbing sound signals which can be generated by the decoding apparatus when the signals received by the telephone become weak and are misread before a cyclic redundancy check circuit detects the error.

Abstract: A method and apparatus for providing loop coherency between a multiplicity of nodes. The disclosed technique and apparatus utilize a primary loop for nominal data communications and a normally unutilized secondary loop. A loop coherency circuit detects a loop incoherency condition which results in a interruption of the primary loop. The loop coherency circuit reroutes the flow of data to a secondary loop segment and back to a primary loop segment to provide a continuous coherent arbitrated loop.

Abstract: A computer system employing an instruction tracing mechanism includes a memory and a CPU. The memory includes a trace buffer used to store records of the instruction tracing. Entries in the trace buffer are pointed to by a tracer pointer. The memory is coupled to the CPU via a bus interface unit. Instructions are passed from the memory to the CPU via the bus interface unit and are queued in an instruction cache, which includes a byte queue. The CPU further includes a control unit coupled to a control register, the tracer pointer and a maskable ROM. The control unit controls and activates the instruction tracing mechanism. In response to software sitting a bit in the control register, the control unit functions to retrieve a special tracing microcode sequence from MROM to provide a trace record of the instructions as they are passed to the instruction decoders. A counting mechanism may also be activated to count instructions and store the count in the memory.

Abstract: Transceivers are selectively activated to reduce power in a network of data processing devices linked by a data transmission loop. Each of the devices is linked by a transceiver, and passes data from a previous device in the loop to a next device in the loop when not transmitting data onto the loop. For example, the data processing devices are disk drives in a storage subsystem. Delays in establishing communication after transceiver activation can be avoided by continuously powering a bit clock oscillator or bit synchronizer. In one embodiment, a loop controller in the loop sends activation and deactivation signals to addressed transceivers via an auxiliary channel. In another embodiment, when a device detects that communication is occurring between other devices for a certain period of time, the device selectively deactivates its transceiver for the certain period of time.