Abstract: Unique Input/Output Sequence (UIO) Sets are constructed to test conformance of a Machine (14) against a Finite State Machine (FSM) model (33). Unique Input/Output Sequence (UIO) Sets (63) uniquely identify FSM model states and may be Forward Unique I/O Sequences (FUIO), Backward Unique I/O Sequences (BUIO), Forward Unique I/O Sequence Sets (FUIOset), and/or Backward Unique I/O Sequence Sets (BUIOset). FSM model (33) state transitions are selected as Edges-Under-Test (EUT). A Set of EUT UIO Sets is identified comprising UIO Sets that uniquely identify either the source or destination FSM model (33) state of an EUT. One member is selected from the Set of EUT UIO Sets for a particular EUT, and each member of this UIO Set is concatenated with the EUT to form Test Subsequences (TS). These Test Subsequences are used to verify that the corresponding FSM transitions are successfully traversed by a Machine Under Test (MUT).

Abstract: An error message is generated by a hardware element of a distributed computer system, when an error is detected. The error message is then forwarded from the hardware element to one or more designated processing nodes of the distributed computer system. The hardware element includes, for instance, a switch element or a communications adapter adapted to report detected errors.