Patents Examined by Pierre Eddy Eliscia
  • Single bus architecture supporting subsystems of various criticality levels
    Patent number: 5841969
    Abstract: Communications systems architecture using a single shared resource bus to interconnect a plurality of subsystems each handling information having a first predetermined importance level and an error detect wrapper for encoding information to and from each such subsystem to detect errors in transmission along the shared resource bus. A heartbeat monitor is also provided for use in those subsystems handling information having a second predetermined level of importance to disable the subsystem if an error occurs within the subsystem.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: November 24, 1998
    Assignee: Honeywell Inc.
    Inventor: James C. Fye