Patents Examined by Pierre Eddy Elisea
  • Patent number: 6081907
    Abstract: A data delivery system facilitates transmission of data packets from a content server to multiple clients over a unidirectional network. A redundancy formatter resident at the server groups multiple data packets into a redundancy group and generates at least one redundancy packet containing redundancy information derived from the data packets in the redundancy group. The data packets and redundancy packet are sent over the unidirectional network to the client. In the event that a packet is lost, a packet rebuilder resident at each client reconstructs the missing data packet from the successfully transmitted data packets in the redundancy group and the redundancy packet for the redundancy group.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: June 27, 2000
    Assignee: Microsoft Corporation
    Inventors: Carl R. Witty, Kenneth J. Birdwell, James Randall Sargent, Brian Moran
  • Patent number: 6049894
    Abstract: In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside a personal computer, built-in test of the personal computer is facilitated.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: April 11, 2000
    Assignee: Adaptec, Inc.
    Inventor: Stillman F. Gates
  • Patent number: 5961646
    Abstract: A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: October 5, 1999
    Assignee: Level One Communications, Inc.
    Inventor: Michael A. Sokol
  • Patent number: 5960171
    Abstract: A compiled cycle based circuit simulator efficiently implements dynamic loop resolution at execution time. A static loop arises when a plurality of signals appear to be interdependent. In a properly designed circuit, apparent looping of signals is usually protected by other mutually exclusive signals. A dynamic loop exists when the signals are actually interdependent. A cyclic clock is divided into a fixed plurality of time slots. During each time slot that a plurality of interrelated signals can change, code for the interdependent signals used by other logic or memory elements are demand generated as function calls. Within each such called function, computation of dependent interdependent signals is by function call protected by control signals. Nondynamic static looping of signals is thus efficiently ignored. Dynamic looping is detected and reported through monitoring of function call depth.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: September 28, 1999
    Inventors: Alan Rotman, Eshel Haritan, Michael L. Braddock, Noam Erdman
  • Patent number: 5951693
    Abstract: A system and method for reconstructing data, and/or generating a parity bit for use in reconstructing data, in a data storage system having a set of disk drives and an associated redundant disk drive. The system includes a memory having an exclusive OR gate to provide an accumulated exclusive ORing of the data successively coupled thereto. The accumulated exclusive OR result is coupled to the redundant disk drive in generating the parity bit or to a replaced disk drive when reconstructing data. The system includes: a bus; a controller coupled between the bus and the disk drives; an addressable memory coupled to the bus. The memory includes: a write buffer memory having an input coupled to the bus; a read buffer memory having an output coupled to the bus; and, the exclusive OR logic unit having a pair of inputs. One input is coupled to an output of the write buffer memory and another input is coupled to the output of the read buffer memory.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: September 14, 1999
    Assignee: EMC Corporation
    Inventors: John K. Walton, Eli Leshem
  • Patent number: 5919257
    Abstract: During pre-boot (i.e., the period of time prior to initiating operation of the workstation operating system), a networked workstation performs an intrusion detection hashing function on selected workstation executable program(s). A computed hash value calculated by the hashing operation is compared against a trusted hash value that is downloaded from a server in order to detect illicit (i.e., authorized) changes to the selected workstation executable programs.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: July 6, 1999
    Assignee: Novell, Inc.
    Inventor: Jonathan Trostle
  • Patent number: 5918009
    Abstract: Using a server system in accordance with the invention, a user and his/her companions can share information on the World Wide Web (WWW). The server system allocates a memory space for storing information particular to the user. This user memory space is associated with the user's login identification (ID) provided to the server system during the user login. Web information obtained by the user from the server system, or a representation of such information, is stored in the user memory space. In sharing the web information, the user's companions need to log onto the server system separately using the user's login ID. The server system then provides the companions with the web information based on the information currently stored in the memory space associated with the user's login ID provided by the companions.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: June 29, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Narain H. Gehani, William D. Roome
  • Patent number: 5870520
    Abstract: A memory system includes a flash ROM for storing the instructions for the BIOS, as well as a flash recovery ROM and a utility for programming both flash ROMs. The memory system also provides for flash disaster recovery in order to enable reprogramming of the BIOS ROM during a condition when the data in the BIOS ROM is found to be corrupt. In particular, the flash recovery ROM is provided with a hardware protected block. Sufficient BIOS instructions (e.g., initialization functions) are provided in the protected area of the flash recovery ROM in order to enable the BIOS ROM to be reprogrammed by way of a flash recovery utility when the BIOS ROM becomes corrupt.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: February 9, 1999
    Assignee: Packard Bell NEC
    Inventors: Min Eig Lee, Jiming Sun