Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.

Abstract: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.

Abstract: In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache Li−1 includes lines of size s and the cache Li includes lines of size t with t>s, a dual line size cache directory mechanism, in which the contents of a cache Li−1 may be accessed at line size granularity s (in which case it is determined whether a line corresponding to a given memory address is stored in Li−1, and if so its location and status), and in which the contents of Li−1 may also be accessed at line size granularity t (in which case it is determined whether any of the t/s lines of size s residing in the larger line of size t corresponding to a given memory address are stored in Li−1, and if so their locations and status) without multiple sequential accesses to a cache Li−1 directory structure.

Abstract: A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner.

Abstract: A peripheral device selected with a chip select is mapped onto address space occupied by DRAM without causing internal or external contentions. A first address range is provided for accessing DRAM. A second address range is provided for accessing another device. The second address range is within the first address range. A row address strobe is provided for accesses within both the first and second address ranges but the column address strobe to the DRAM is inhibited when a memory access occurs within the second address range.

Abstract: Identifying most recent redundant copies of identifiable data volumes stored in a plurality of data storage libraries which are coupled to a plurality of directors. To update a data volume, an initiating director attempts to set a current token “inconsistent” flag to potentially down level copies of the data volume on each lagging library. Upon failing to receive notification of any successful setting of the current token “inconsistent” flag from any of the lagging libraries, the director forwards the request to the other directors, which attempt to set the current token “inconsistent” flag for the volume at any lagging library from which no notification has been received. Upon all of the other directors responding to the initiating director, and upon the other directors indicating failure to set the “inconsistent” flag at the lagging library, all the directors list the volume and a new token as an entry in a “hot token” list.