Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

Abstract: An interface control system located between a PC and a CD-ROM includes an address selector, a first control signal generator, a second control signal generator, a bus transceiver, a control information transmitter, a read/write signal generator and a command/reset signal generator and interfaces between a host computer and a CD-ROM driver by a memory mapped I/O method using an ISA BUS standard.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A method for operating a local device to permit a host computer to assert control over the local device via a communication port. A control available time window of prearranged duration is set up in the local device in response to a power on start condition. During this control available time window an Assert Control signal is received from the host computer. An Acknowledge Control signal is sent to the host computer upon receipt of the Assert Control signal during the control available time window. Then the local device responds to any control commands and data received from the host computer. Finally, the local device initiates processing of a normal local device application processes when no Assert Control signal is received during the control available time window or after the host computer has finished sending control commands and data to the local device.

Abstract: An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.

Abstract: In a computer system having a computer connected to peripheral devices, an illumination device is connected via a termination data line to a selected peripheral device. The illumination device provides illumination when current is supplied via the termination data line, thereby indicating the presence of at least one terminator in the peripheral devices. A second illumination device may be connected to the selected peripheral device via an overtermination data line and a termination power line for indicating the presence of more than one terminator among the peripheral devices when current supplied via the overtermination data line exceeds a threshold amount. A third illumination device may also be connected via the termination power line for indicating the presence of termination power when current is supplied via the termination power line.