Abstract: Automatic tracking and assembly of changed portions of configuration data for partial run-time reconfiguration of a programmable logic device (PLD). The methods of an API that supports run-time reconfiguration applications for a PLD manage configuration data for partial reconfiguration. The API saves in application memory a copy of the configuration data used to configure the PLD. As the application updates selected portions of the in-memory configuration data, the API tracks which portions of the configuration data changed. When the application initiates reconfiguration of the PLD, the API partially reconfigures the PLD with the tracked changed portions of the configuration data. For readback of configuration data from the PLD, the API tracks which portions of in-memory configuration data are synchronized with the PLD.

Abstract: The present invention relates to a method for the synchronization of a first and a least one second module, each having a clock generator. The invention furthermore relates to such modules, a master program module, a slave program module and a device for this purpose. It is proposed that the first module, transmits a first clock signal generated by its clock generator to the second module, which synchronizes its clock generator with the first clock signal. The second module transmits a second clock signal generated by its clock generator that is synchronized with the first clock signal to the first module, which determines a time difference value between the first clock signal and the second clock signal, which time difference value is essentially due the transmission time of the first and the second clock signal between the first and the second module.

Abstract: The invention provides, in an embodiment, a structure, method and means for generating clock phases, synchronized to the system clock, that to first order are independent of process parameters including drive current, parasitic resistance and parasitic capacitance. In one aspect, an apparatus is provided to generate an output phase at a predetermined time relative to an input clock signal and dependent on a logic phase width of the input clock signal. In another aspect, the apparatus includes similar circuit components with unequal units, the predetermined time is further dependent on the units ratio of the similar circuit components. In another aspect, the apparatus is cascaded with at least one reproduction of the apparatus, and configured to provide a multiple of the input clock signal. In another aspect, the apparatus is coupled in parallel with at least one reproduction of the apparatus, and configured to provide at least two output phases generated in parallel during the input clock signal.

Abstract: The invention relates to a computer in which an image of the operating system is maintained in a secondary memory. This memory is either powered from a source independent of the main memory, or is non-volatile in nature. When the computer is reinitialized, the loader software that normally builds the operating system from components instead checks the secondary memory for the presence of an operating system image. If such an image is detected, the loader transfers the image from the secondary memory to the primary memory and transfers control of the computing system to the image of the operating system now in the primary memory. If no image is detected, the loader operates in a standard fashion. Additionally, a complete system image may be stored in the secondary memory. This would include the contents of the primary memory, the contents of the virtual memory, and the system state. As such, a preexisting version of an operational computing system may be directly loaded at boot time.

Abstract: A circuit for generating a start pulse signal for a source driver IC in a TFT-LCD includes: a first latch unit for receiving a data enable signal and a reset signal, extracting a leading edge of the data enable signal in a leading edge of a main clock signal, and latching the data enable signal in a trailing edge thereof; a logic gate unit for receiving a complementary signal of the output signal from the first latch unit and the data enable signal, and generating a pulse signal in a leading edge of the data enable signal; and a second latch unit for receiving the output signal from the logic gate unit and the reset signal, outputting the output signal from the logic gate unit as a start pulse signal in the leading edge of the main clock signal, and latching the output signal from the logic gate unit in the trailing edge thereof.

Abstract: Method and system for latency-independent peripheral device identification. In one embodiment, a computer system receives an interrupt from a peripheral device coupled to a computer system communications port. In response, an interrupt notification message is posted alerting a notification handler running on the system. It is determined whether the interrupt is indicates peripheral class compliance. In one embodiment, communications port device sense pin voltage is determinative. If the interrupt indicates peripheral class compliance and the communications port is inactive, the port is opened, and inquiry sent to the peripheral device via the open port. The computer system then waits for response from the peripheral device. If response is received within a predetermined time, identification is posted based on the response, including peripheral device classification information, so that a software handler registered with the operating system can handle the identification message when received.