Abstract: A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.

Abstract: According to one embodiment, a display device includes a first lower electrode and a second lower electrode disposed on a first insulating layer, a partition wall connected to a pixel circuit, a first organic layer disposed on the first lower electrode and a first upper electrode disposed on the first organic layer. The partition wall includes a conductive layer and a second insulating layer. The conductive layer is a portion connected to the pixel circuit, and includes a first side surface opposing the first lower electrode and a second side surface opposing the second lower electrode. The second insulating layer is disposed on the conductive layer. The first lower electrode is in contact with the first side surface and the second lower electrode is spaced apart from the second side surface.

Abstract: The present application provides a manufacturing method of a transistor, including: providing a substrate, a solution, an active layer material and an auxiliary electrode; the active layer material is dispersed in the solution, and the active layer material is charged; positioning the auxiliary electrode on one side of the substrate; positioning the solution between the auxiliary electrode and the gate insulating layer; and electrifying the gate and the auxiliary electrode; an electrical property of the gate is opposite to an electrical property of the active layer material, and the active layer material is deposited on the gate insulating layer under an action of the electric field to form a source layer.

Abstract: Provided are display panel and display device. Display panel includes base substrate; light-emitting element located on base substrate; first electrode and second electrode both electrically connected to light-emitting element, both located on side of light-emitting element facing base substrate or on side of light-emitting element facing away from base substrate and both providing voltage signals for light-emitting element; first reflective layer located on side of light-emitting element facing base substrate, and with direction perpendicular to base substrate as projection direction, first reflective layer covering light-emitting element; and voltage signal line located on side of light-emitting element facing base substrate. First electrode and second electrode respectively include first extension part and second extension part, at least one of which is connected to voltage signal line and does not overlap first reflective layer.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate, a body well in the semiconductor substrate, a source region in the body well, a drain well in the semiconductor substrate, a drain region in the drain well, and a gate electrode laterally positioned between the source region and the drain region. The drain well includes an edge adjacent to the body well, and the edge of the drain well has a spaced relationship with the body well.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: Embodiments of the present disclosure relate to a light-emitting device package and an electronic device. In an embodiment, a light-emitting device package is provided that includes a lead frame, at least two light-emitting devices mounted on the lead frame and configured to emit different wavelengths of a same color of light, and a phosphor configured to emit light having a color different from the color of light emitted from the at least two light-emitting devices. The embodiments of the present disclosure also relate to an electronic device including the light-emitting device package as a light source. According to the embodiments of the present disclosure, various expressible color spaces can be selectively expressed.

Abstract: An image pickup device having a pixel region in which pixels are arranged, and in which a multilayer wiring structure is disposed. Each pixel includes a photoelectric conversion unit, a charge accumulation unit, a floating diffusion, a light shielding portion covering the charge accumulation unit and opening above the photoelectric conversion unit, and a waveguide which overlaps at least partially a portion at which the light shielding portion opens in a plan view. The device includes an insulating film disposed below the optical waveguide. The insulating film has a refractive index higher than that of an interlayer insulating film. The insulating film is disposed closer to the photoelectric conversion unit than to the lowermost wiring layer among wiring layers of the multilayer wiring structure. The insulating film extends to a portion above the light shielding portion. The insulating film is wider than a lower portion of the optical waveguide.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device may include a pixel circuit layer including a plurality of transistors, a first partition wall and a second partition wall on the pixel circuit layer, and each protruding in a thickness direction, a first electrode and a second electrode formed on the same layer, and on the first partition wall and the second partition wall, respectively; a light emitting element between the first electrode and the second electrode; and a first organic pattern directly on the light emitting element.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Abstract: A light emitting device including first, second, and third light emitting stacks each including first and second conductivity type semiconductor layers, a first lower contact electrode in ohmic contact with the first light emitting stack, and second and third lower contact electrodes respectively in ohmic contact with the second conductivity type semiconductor layers of the second and third light emitting stacks, in which the first lower contact electrode is disposed between the first and second light emitting stacks, the second and third lower contact electrodes are disposed between the second and third light emitting stacks, and the first, second, and third lower contact electrodes include transparent conductive oxide layers.

Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Abstract: Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure.

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Abstract: An electronic device includes a first substrate, a circuit layer, a conductive wire, and an adhesive layer. The first substrate has a first surface, a second surface and a first side surface. The second surface is opposite to the first surface, the first side surface is located between the first surface and the second surface, and the first side surface connects the first surface and the second surface. The circuit layer is disposed on the first surface of the first substrate. The conductive wire is electrically connected to the circuit layer. The adhesive layer is disposed on the first surface and the circuit layer. The adhesive layer has a second side surface, and a first portion of the conductive wire is disposed on the first side surface of the first substrate and the second side surface of the adhesive layer.

Abstract: A display device and a method of fabricating the same are provided. The display device includes a substrate, a first electrode on the substrate, a second electrode on the substrate and spaced apart from the first electrode, a plurality of light emitting elements, at least a portion of each of which is between the first electrode and the second electrode, and contact electrodes on the first electrode, the second electrode and the light emitting elements, the contact electrodes including a conductive polymer, wherein the contact electrodes include a first contact electrode which contacts an end portion of a first portion of the light emitting elements and the first electrode and a second contact electrode which contacts an end portion of a second portion of the light emitting elements, and the second electrode and is spaced apart from the first contact electrode.

Abstract: A method for making a micro-LED display panel includes providing a substrate; transferring micro-LEDs on a surface of the substrate; transferring conductive blocks on the surface of the substrate having the micro-LEDs; forming an insulating layer to cover the micro-LEDs and the conductive blocks; forming upper electrodes, each of the upper electrodes covering a surface of one of the micro-LEDs away from the substrate; and forming top wires on a surface of the insulating layer away from the substrate.

Abstract: A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.