Abstract: Disclosed is an automated method and system for upgrading an automation function controlling an actuator via a PLC (programmable logic controller), including: providing a first container and a first sidecar container, whereby the first container contains a first automation function, the first automation function is controlling the actuator via the PLC, providing a second container and a second sidecar container, whereby the second container contains a second automation function, the second automation function is receiving data from the actuator but is not controlling the actuator, based on the received data pre-activation tests for the second automation function are executed in the second sidecar container by the second test unit, if the pre-activation tests are successfully finished, the time when the control of the actuator is handed over is determined, and the control of the actuator is handed over from the first automation function to the second automation function.

Abstract: A method and system are disclosed for testing functionality of a software program based on at least one modification to a software code of the software program. In one embodiment, the method includes: receiving software code of software program from one or more sources; identifying functions within the software code of the software program affected by the modification of software code; simulating the identified functions of the software program using digital twin; determining workflows of the software program based on the simulation of digital twin; identifying at least one impacted workflow from determined workflows based on one or more requirements of software program; and executing at least one impacted workflow critical to the functionality of the software program for testing the functionality of software program.

Abstract: Provided are a compiling device, a compiling method, and a compiling program with which the speed of a program can be increased when a loop in a program includes an access to adjacent data. The compiling device includes: a loop analysis unit for determining whether vectorization of a loop in a source program is possible when an access to adjacent data is included in the loop; and a vectorization execution unit for generating an instruction for reading elements required for computation from a memory to a vector register when access to the adjacent data is included and the vectorization of the loop is possible.

Abstract: Techniques for program code management are disclosed. For example, a method obtains resource utilization data from a computing network comprising a plurality of computing devices. The method then utilizes a multi-variate time series model representing at least a portion of the resource utilization data to automatically compute at least one time window in which to perform a program code update on at least a subset of the plurality of computing devices.

Abstract: The technologies described herein provide a system having nonvolatile firmware memory that is configured on the same integrated circuit as a BMC SoC. This design provides the ability to store the system firmware within the SoC to minimize or eliminate the use of complex components or specialized silicon, while minimizing the number of attack points. The disclosed techniques also improve the performance of a system by eliminating the need for a system to perform a validation of contents stored on an external memory device for each boot. Further, the disclosed techniques can allow a storage device that is internal to the SoC to use a local bus of the SoC, and mitigate or eliminate the need for an SPI bus, which is much slower than the local bus of the BMC SoC.

Abstract: An apparatus to facilitate data parallel programming task graph optimization through device telemetry is disclosed. The apparatus includes a processor to: receive, from a compiler, compiled code generated from source code of an application, the compiled code to support a workload of the application; generate a task graph of the application using the compiled code, the task graph to represent at least one of a relationship or dependency of the compiled code; receive runtime telemetry data corresponding to execution of the compiled code on the one or more accelerator devices; identify one or more scheduling optimizations for the one or more accelerator devices based on the task graph and the received telemetry data; and provide a scheduling command to cause the one or more scheduling optimizations to be implemented in the one or more accelerator devices.

Abstract: A method includes: acquiring a hook point and a virtual program counter by analyzing a virtual machine of a script engine; acquiring a branch virtual machine instruction by analyzing an instruction set architecture; and providing an analysis function to the script engine based on the acquired virtual program counter and the acquired branch virtual machine instruction, wherein the analysis function is provided by applying a hook to the acquired hook point and wherein the hook includes processing of, in response to an occurrence of an exception, changing a pointing destination of a virtual stack pointer to a return destination of a function immediately before a part where the exception has occurred.

Abstract: In one embodiment, a method includes receiving information associated with a plurality of devices. The information includes a manufacturer, a model name, and a current version of software for each of the plurality of devices. The method also includes generating a plurality of classifications. Each of the plurality of classifications is associated with a particular manufacturer and a particular model name. The method further includes determining a number of the plurality of devices in a first classification of the plurality of classifications, categorizing the number of the plurality of devices in the first classification into a plurality of categories by the current version of software, and determining, independent of any type of device identifier, a latest available version of software for the first classification.

Abstract: Compiler techniques lot inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.

Abstract: A method for pipeline parallelism compiling is provided, which is executed by one or more processors, and includes receiving a source program associated with training of a machine learning model, determining, based on the source program, a plurality of operation groups including operations executed on training data of the machine learning model, generating a plurality of micro-batches from the training data, and determining, for each of the plurality of micro-batches, a plurality of operation sets corresponding to the plurality of operation groups.

Abstract: An AI tool for writing computer code is generated by collecting code entry data from a plurality of remote computing devices, training a code completion network using the code entry data, wherein the code completion network is configured to predict one or more additional code entry activities based on a provided set of code entry activities, and providing the code completion network to one or more development sessions. A code segment is intelligently generated by receiving a request to modify computer code of a program in a development interface, and presenting a text input component and a code description prompt. The technique further includes receiving, via the text input component, a code description, applying at least part of the code description to a code generation network to obtain a code segment suggestion and presenting the code segment suggestion on a display.

Abstract: An AI tool for writing computer code is generated by collecting code entry data from a plurality of remote computing devices, training a code completion network using the code entry data, wherein the code completion network is configured to predict one or more additional code entry activities based on a provided set of code entry activities, and providing the code completion network to one or more development sessions. A code segment is intelligently generated by receiving a request to modify computer code of a program in a development interface, and presenting a text input component and a code description prompt. The technique further includes receiving, via the text input component, a code description, applying at least part of the code description to a code generation network to obtain a code segment suggestion and presenting the code segment suggestion on a display.

Abstract: Provided is a program and computer-implemented method of obfuscating a software code, comprising adding a conditional branch instruction to the software code which, when executed, causes evaluating an opaque predicate (PT, PF, P?). The method comprises a step of generating the opaque predicate which includes performing a multiplication operation having as operands two mixed Boolean-arithmetic expressions. Other embodiments disclosed.

Abstract: Various embodiments described herein support or provide operations including receiving input data that comprises a collection of data units; determining that the collection of data units corresponds to a number of tokens that exceeds an upper limit of tokens; processing the collection of data units to generate a plurality of outputs; and aggregating the plurality of outputs into a final result provided as output of a function.

Abstract: A method for inference performance in an artificial intelligence model provides reduction of pre-processing overhead. The method includes receiving a plurality of operations associated with the artificial intelligence model. A computational graph for the artificial intelligence model is generated. Each of the operations is categorized into one of three categories including: accelerator designated operations, central processing unit (CPU) designated operations, and undetermined processing designated operations. An estimated processing time is determined for the operations. The operations are inserted into the computational graph. The computational graph is divided into sub-graphs. Edges of the sub-graphs where pre-processing steps will be performed is determined.

Abstract: A storage device management system (SDMS) as a component of an application acceleration system; this is for managing AppAccel hardware storage devices (AI hardware SDs) using a distributed hardware F+ Update Server service layer of one or more hardware F+ Update Servers managing a storage set of one or more AI hardware SDs. The one or more hardware F+ Update Servers manage the one or more AI hardware SDs with mechanisms such as SyncLink, data paths, SC Program Store, etc. having multiple uses among which is interoperating with AI hardware SD management components of the one or more hardware F+ Update Servers. The SDMS is composed of the one or more hardware F+ Update Servers and employ these mechanisms on one, many, or all of the one or more AI hardware SDs to enable feedback to the SDMS, which is an important operative part of managing one, many, or all of the one or more AI hardware SDs.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for selection of ranked configurations.

Abstract: A method includes generating an ablation programming language, which defines commands for (i) setting ablation protocol parameters and respective values, (ii) setting a configuration of an ablation system, (iii) applying automatic logic that relates the ablation protocol parameters and the values to the configuration of the ablation system, and (iv) generating one or more graphical user interfaces (GUIs) showing one or more of the parameters of the ablation protocol and the system configuration. The ablation programming language is provided for subsequent use with the ablation system.

Abstract: Disclosed herein are techniques for providing comparative performance metrics to software application developers.

Abstract: A computer-implemented method, system and computer program product for performing user acceptance testing. A virtual environment for virtual sponsor users to interact with a feature or a function of a software product is created. Such virtual sponsor users are virtual representations of actual or real sponsor users. Each of these virtual sponsor users are then assigned a persona type profile of a target audience. Such persona type profiles include the character traits of a user, such as a user or member of the target audience. Interactions of the virtual sponsor users with the feature or the function of the software product are then simulated and tracked. The rate of acceptance of the feature or the function of the software product is then determined based on such tracked interactions. In this manner, user acceptance testing is performed in a swiftly manner that is cost effective.