Abstract: An FM signal oscillator circuit includes a resonator having a graded- or abrupt-junction variable capacitance diode that is producible through standard IC manufacturing processes but causes an inconstant modulation level. The FM signal oscillator circuit, therefore, is provided with a function of maintaining a constant modulation level irrespective of oscillation frequencies. Namely, to maintain a constant modulation level without regard to oscillation frequencies that change depending on a control voltage applied to the variable capacitance diode, the FM signal oscillator circuit employs a variable gain amplifier whose gain changes in response to the control voltage. The variable gain amplifier amplifies a modulating signal, and the amplified modulating signal is superimposed onto the control voltage.

Abstract: A double-gated low power active clamp circuit for digital circuits includes a first double-gated MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second double-gated MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second double-gated MOSFETs are held at constant reference voltages by a single or double reference circuits. The clamping action can be switched on or off. The double-gated active clamping network can be implemented with a single power supply voltage, or with multiple power supply voltages. The use of the back gates of the double-gated active clamping network enables additional clamping and ESD protection for smaller generations of transistors, such as, those having dimensions below 0.1 micron. The device is particularly suited for use with dynamic threshold double-gated silicon-on-insulator, FINFET, and bulk triple well technologies.

Abstract: An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection.

Abstract: A temperature-compensated diode rectifier circuit is coupled to the outside of an HF amplifier (PA) to derive a rectified voltage (UD) from an HF output signal (RFOUT) with a rectifier input (IR) via a directional coupler (D-CO) with secondary connections (1, 2), and has a rectifier output (OR) for the rectified voltage (UD), a rectifier diode (D1), a charging capacitor (C1) and a ballast resistor (R2). To stabilize the rectified voltage against temperature influences, the rectifier input (IR) is connected to a d.c. input voltage (UIN), and a compensating diode (D2) is in series with the ballast resistor (R2), and a dropping resistor (R1) is in series with the rectifier diode (D1). According to the invention the rectifier diode (D1), the compensating diode (D2), the dropping resistor (R1), the ballast resistor (R2) and the directional coupler (D-CO) are connected to the d.c. input voltage (UIN) so that the voltage amplitude of the decoupled HF output signal (RFOUT) is added to the d.c. input voltage (UIN).

Abstract: The function module enables generation of a second current which has a relationship to at least one first current of the type y=xk/j, in which x is the value of the first current and y is the value of the second current, k and j being respective different positive integers which can be freely selected. It comprises a series of sections (C1, C2, . . . , Cj, . . . ), each section comprising a variable conductance (G*j) whose value is proportional to the current flowing in the variable conductance of the section which preceded this section in the series. The conductance (G*1) of the first section is proportional to a reference current (I0).

Abstract: Boost circuit units are connected in parallel. A boost output voltage VBOOST′ of a dummy boost circuit unit having the same configuration as the boost circuit units is detected by a voltage detection circuit. The voltage detection circuit outputs a signal TBST2 which becomes “high” when VBOOST′ is lower than VLIMIT and “low” when VBOOST′ is equal to or higher than VLIMIT. The TBST2 signal is input to a NAND circuit. When a “high” signal is input to the NAND circuit, an input voltage ATDBST2 is input to the boost circuit unit as well via the NAND circuit and the two boost circuit units perform boost operation. Thus, a boost circuit can suppress the dispersion of the boost voltage caused by the dispersion of the process condition and the variation of the external temperature besides the variation of the power supply voltage Vcc.

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.