Patents Examined by Quinton A Brasfield
  • Patent number: 11122216
    Abstract: A first pixel circuit has a plurality of photodiodes of different sizes. A second pixel circuit is connected to the first pixel circuit, and has a holding portion that holds a first optical signal and a second optical signal. The peripheral circuit drives and controls the second pixel circuit, and determines whether a voltage value of the first optical signal is equal to or greater than a predetermined value. When it is determined that the voltage value of the first optical signal is equal to or greater than the predetermined value, a signal obtained by adding the second optical signal to the first optical signal is set as an output signal. When it is determined that the voltage value of the first optical signal is less than the predetermined value, the first optical signal is set as an output signal.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Masaki Funaki
  • Patent number: 11117800
    Abstract: A device preferably for use in an inertial navigation system the device having a single IC wafer; a plurality of sensors bonded to bond regions on said single IC wafer, at least one of said bond regions including an opening therein in gaseous communication with a pressure chamber associated with at least one of the plurality of said sensors; and a plurality of caps encapsulating said plurality of sensors, at least one of said plurality of caps forming at least a portion of said pressure chamber. A method of making the device is also disclosed.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 14, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Deborah J. Kirby, Raviv Perahia, Hung Nguyen, Frederic P. Stratton, David T. Chang
  • Patent number: 11121207
    Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Abbas Ali, Sopa Chevacharoenkul, Jarvis Benjamin Jacobs
  • Patent number: 11101199
    Abstract: A power semiconductor device is such that a notch provided, along a longitudinal end face of an inner lead, in a region of a lead frame to which the inner lead is bonded. A resistor is disposed, adjacent to the inner lead, on the same side as the notch with respect to the inner lead, and a distance between the inner lead and the notch is set to be smaller than a distance between the inner lead and the resistor, and thereby the inner lead, even when shifted in position, comes into no contact with the resistor. Because of this, it is no more necessary that a space be provided around the inner lead taking into consideration a positional shift of the inner lead, and it is possible to secure the heat release area of power semiconductor chips accordingly, and thus to obtain the small-sized and high-powered power semiconductor device.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Saburo Tanaka, Tatsuya Fukase, Masaki Kato, Norio Emi
  • Patent number: 11094579
    Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Patent number: 11088244
    Abstract: Examples herein relate to devices having substrates with selective airgap regions for mitigating defects resulting from heteroepitaxial growth of device materials. An example device may include a first semiconductor layer disposed on a substrate. The first semiconductor layer may have a window cut through a face, where etching a selective airgap region on the substrate is enabled via the window. A second semiconductor layer may be heteroepitaxially grown on the face of the first semiconductor layer so that at least a portion of the second semiconductor layer is aligned over the selective air gap region.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 10, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Di Liang
  • Patent number: 11056436
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 11049828
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 29, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
  • Patent number: 11043449
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and having the active surface disposed on the connection structure to face the connection structure, and an encapsulant covering at least a portion of the semiconductor chip, wherein the semiconductor chip includes a groove formed in the active surface, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Woo Myung, Ha Kyeong Lee, Hyun Mi Kang
  • Patent number: 11031547
    Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Ru-Ying Tong
  • Patent number: 11031358
    Abstract: A method for forming a sensor with increased overhang to prevent passivation stress fractures is provided. Embodiments include forming a first passivation layer over a dielectric layer patterned over a first top metal layer of a logic region of a sensor and a second top metal layer of an array region of the sensor; planarizing the first passivation layer and the dielectric layer to form a level surface above the first top metal layer and the second top metal layer; etching the dielectric layer to form a pad opening in the array region of the sensor based on a predetermined overhang value, the pad opening exposing a portion of the surface of the second top metal layer; and forming a second passivation layer over the level surface and the pad opening in the array region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Aarthi Sridharan, Gong Cheng, Premachandran Chirayarikathuveedu, Fahad Mirza, Carole Graas, Sricharan Tubati, Nurul Islam Mohd
  • Patent number: 11031286
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 11031371
    Abstract: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 8, 2021
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin Tien Chiu, Tiger Tai, Ken Qian, C C Liao, Hem Takiar, Gursharan Singh
  • Patent number: 11018218
    Abstract: The present disclosure, in some embodiments, relates to a method of semiconductor processing. The method may be performed by etching a substrate to define a trench within the substrate. A sacrificial material is formed within the trench. The sacrificial material has an exposed upper surface. A plurality of discontinuous openings are formed to expose separate segments of a sidewall of the sacrificial material. The plurality of discontinuous openings are separated by non-zero distances along a length of the trench. An etching process is performed to simultaneously etch the exposed upper surface and the sidewall of the sacrificial material.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Te-Hao Lee
  • Patent number: 11011601
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate. As viewed from a top-view, the substrate has a first sidewall, one or more second sidewalls, and a plurality of third sidewalls. The first sidewall extends along a first direction and defines a first side of a trench. The one or more second sidewalls extends along the first direction and define a second side of the trench. The plurality of third sidewalls are oriented in parallel and extends in a second direction perpendicular to the first direction. The plurality of third sidewalls protrude outward from the second side of the trench and define a plurality of parallel releasing openings that are separated along the first direction by the substrate. The trench continuously extends in opposing directions past the plurality of parallel releasing openings.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Te-Hao Lee
  • Patent number: 10978548
    Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu
  • Patent number: 10964689
    Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 30, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jui-Fa Lu, Chien-Nan Lin, Ching-Hua Yeh
  • Patent number: 10937782
    Abstract: An electrostatic discharge, ESD, protection structure (200) formed within a semiconductor substrate of an integrated circuit device (600). The integrated circuit device (600) comprising: a radio frequency domain (632); a digital domain (610). The ESD protection structure (200) further includes an intermediate domain located between the radio frequency domain (632) and the digital domain (610) that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 2, 2021
    Assignee: NXP B.V.
    Inventors: Dolphin Abessolo Bidzo, Janusz Tomasz Klimczak, Detlef Clawin, Radu Mircea Secareanu
  • Patent number: 10937956
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10916491
    Abstract: A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)<1 holds, where A and B are the tensile strength of the first and second solder, respectively. As a result, even if the lead terminal which thermally expands because of heat generated by the semiconductor element expands or contracts toward the semiconductor element, a stress applied by the lead terminal is absorbed and relaxed by the first solder. This prevents damage to the surface electrode of the semiconductor element by suppressing the occurrence of cracks.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Kohei Yamauchi, Hiromichi Gohara, Tatsuhiko Asai