Abstract: Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a perimeter of the casing, and the second electrode can extend away from the chip carrier part and projects outside of the casing. In extending away from the chip carrier part the first electrode divides into a plurality of leads separated by an aperture that join into a single first joined lead portion with a first width before projecting outside of the casing and maintains the first width outside of the casing. The second electrode can attain a second width prior to projecting outside of the casing and maintains the second width outside the casing.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric layer, electrically coupled to the gate to form continuous multigate transistors.

Abstract: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.

Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.

Abstract: A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

Abstract: The present invention provides the following methods and displays. A method for manufacturing an EL display panel, having the step of forming a light-emitting layer by irradiating light on a photothermal conversion layer through a transparent base member while a dye layer of a transfer member having the transparent base member, the photothermal conversion layer and this fluorescent dye layer is kept in close contact with an object to which the dye is to be transferred, the transparent base member, the photothermal conversion layer and the transfer member being laminated in this order, so that the dye can be transferred to the object. An EL display panel produced according to this method, an image display having this panel, and a method for manufacturing the image display.

Abstract: Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide.

Abstract: A chip package including a substrate, a chip and a mark is provided. The substrate has a carrying surface. A mark region is disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the substrate. The mark is disposed in the mark region for recording a process parameter.

Abstract: The present invention is to provide a semiconductor device which includes a mounting base and a light-emitting device. The mounting base includes a substrate of a first semiconductor material and a first layer of a material with high thermal conductivity formed over the substrate. Furthermore, the light-emitting device is a multi-layer structure which includes at least a second layer of a second semiconductor material. The light-emitting device is mounted on the first layer of the mounting base. Moreover, the difference of the thermal expansion coefficient between the first semiconductor material and the second semiconductor material is between a predetermined range.

Abstract: An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.

Abstract: It is an object of the present invention to manufacture, with high yield, semiconductor devices in each of which an element which has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming an element-forming layer by forming an inorganic compound layer, a first conductive layer, and a layer containing an organic compound over the separation layer, and forming a second conductive layer which is in contact with the layer containing an organic compound and the inorganic compound layer; and after attaching a first flexible substrate over the second conductive layer, separating the separation layer and the element-forming layer at the separation layer.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a pad oxide layer on a semiconductor substrate, forming a pad nitride layer on the pad oxide layer, forming a capping layer on the pad nitride layer, patterning the capping layer, the pad nitride layer, and the pad oxide layer by a photolithography method to expose portions of the semiconductor substrate, forming a field oxidation layer having bird's beaks, the bird's beaks being formed under the pad nitride layer, forming trenches in the semiconductor substrate by anisotropically etching the field oxide layer and the semiconductor substrate using the pad nitride layer as a mask, removing the capping layer, the pad nitride layer, the pad oxide layer, and the bird's beaks, and forming an isolation region in the trenches.

Abstract: A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into contact with the passivation film; a resin layer formed on the first metal layer; a wiring formed so as to be electrically coupled to the electrode and reach an upper surface of the resin layer; and a second metal layer formed so as to be in contact with the first metal layer and reach the upper surface of the resin layer.

Abstract: The invention includes new organic-containing compositions that can function as an antireflective layer for an overcoated photoresist. Compositions of the invention also can serve effectively as a hard mask layer by exhibiting a sufficient plasma etch selectivity from an undercoated layer. Preferred compositions of the invention have a high Si content and comprise a blend of distinct resins.

Abstract: Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are sequentially formed in the trench and/or via hole. Portions of the metal layer, the barrier metal layer and the interlayer insulating layer are removed. After that, the combined thickness of the two or more insulating layers is measured again.

Abstract: In a method of manufacturing a semiconductor device having a through electrode 56 that connects an electrode pad 20 of a semiconductor element 14, which has a device forming layer 18 and the electrode pad 20 on one surface side, and a rewiring pattern 52 on other surface side of the semiconductor element 14, the device forming layer 18 and the electrode pad 20 are formed on an upper surface side of the semiconductor element 14, a first resist layer 62 is formed on surfaces of the electrode pad 20 and the device forming layer 18, an opening 64 is formed in the electrode pad 20 by the etching, and a through hole 54 is formed in the semiconductor element 14 by the etching in a position that is communicated with the opening 64. The device forming layer 18 is protected by the first resist layer 62, and also a flip-chip connection can be applied by providing the through electrode 56 to attain a downsizing.

Abstract: A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a capacitor electrode. An ion implantation is conducted on the polysilicon layer to form drain and source electrodes. A second dielectric layer and a second patterned metal layer are formed thereon. Sequentially, a third dielectric layer is formed thereon. A plurality of via openings are formed by a patterned photoresist layer, and a third metal layer is formed thereon and filled into the via openings. The patterned photoresist layer and the redundant third metal layer are stripped from the substrate to form via plugs in the via openings. A patterned transparent conductive layer is formed thereon to connect the via plugs.

Abstract: Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.