Abstract: A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on the dielectric layer comprising silicon and carbon. The dielectric layer may comprise a first dielectric layer comprising silicon, carbon, and nitrogen, and a second layer of nitrogen-free silicon and carbon containing material in situ on the first dielectric layer, and a third dielectric layer comprising silicon, oxygen, and carbon on the second dielectric layer.

Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

Abstract: An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type.

Abstract: Comparing with, for example, a semiconductor device having the configuration in which the logic circuit and the DRAM cell circuit are consolidated, a semiconductor device in which an analog capacity element is installed without substantially increasing the number of the steps is provided. An analog capacity element to be installed in the DNA e11 circuit has a structure in which a lower electrode 5, a side-wall insulation film 9, and a bit line are formed using the same materials and the same patterns as those of a gate electrode 4, a dielectric film 10, and bit line, respectively.

Abstract: The invention provides processes for producing a high-quality silicon dioxide layer on a germanium layer. In one example process, a layer of silicon is deposited on the germanium layer, and the silicon layer is exposed to dry oxygen gas at a temperature that is sufficient to induce oxidation of the silicon layer substantially only by thermal energy. In a further example process, the silicon layer is exposed to water vapor at a temperature that is sufficient to induce oxidation of the silicon layer substantially only by thermal energy. It can be preferred that the exposure to dry oxygen gas or to water vapor be carried out in an oxidation chamber at a chamber pressure that is no less than ambient pressure. In one example, the chamber pressure is above about 2 atm. The temperature at which the silicon layer is exposed to the dry oxygen gas is preferably above about 500° C., more preferably above about 600° C., even more preferably above about 700° C., and most preferably above about 800° C.

Abstract: The problem of stress transmission from the outside of an integrated circuit package into the interior of the semiconductor has been significantly reduced by placing a micro-spring between the external solder ball and the interior tab. The process for manufacturing such a structure begins with a fully completed integrated circuit on whose surface freestanding metal posts are formed, each post being in contact with an I/O pad. Using a leveling plate at elevated temperature, the posts are given a permanent tilt relative to the surface and are then encapsulated in an elastomer. This subprocess may then be repeated as many times as desired with the direction in which the posts lean being changed by 90 degrees at each iteration. This results in the formation of an orthogonal spiral which acts as a coil spring to absorb stress originating at the solder ball.

Abstract: For fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric. A drain silicide is formed in the drain region, and a source silicide is formed in the source region. The drain and source silicides have a first silicide thickness. A first dielectric layer is conformally deposited over the drain region, the source region, and the gate and is polished down until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon gate structure are exposed. The capping layer on the polysilicon gate structure of the gate is etched away such that the top of the polysilicon gate structure is exposed.

Abstract: A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials.

Abstract: A method of substantially reducing stress in a trench comprising forming at least one trench in a substrate, said substrate having a surface; filling the at least one trench with a trench dielectric material; planarizing the filled trench stopping on said surface of said substrate; and subjecting the planarized trench to an anneal step, said anneal step being carried out under rapid thermal conditions at a temperature of about 800° C. or above and in the presence of an atmosphere comprising hydrogen.

Abstract: In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.

Abstract: A method for forming a titanium dioxide layer is disclosed. The method includes the steps of providing a titanium-containing material, adding an acid substance to the titanium-containing material to form a mixture, and exposing the device to the mixture to form the titanium dioxide layer thereon. Such a method can be applied for forming a titanium dioxide layer on a semiconductor device, a silicon substrate, an integrated circuit, a photoelectric device, etc.