Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

Abstract: A schottky junction diode is provided by a substrate (32) having a mesa stacked thin horizontal semiconductor layer (34, 50) with an exposed edge (36) at a generally vertical side (38) of the mesa, and a schottky metal layer (40) having a generally vertical portion (42) over the semiconductor layer edge and forming a generally vertical schottky junction (44) having an area in 10.sup.-8 to 10.sup.-10 cm.sup.2 range for operation at millimeter and submillimeter wave frequencies.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.

Abstract: A solid-state photosensitive device for detecting electromagnetic radiation comprises N photosensors connected through a transition zone to a reading device of the charge-coupled type. The reading device features two charge-coupled shaft registers having N/2 parallel inputs and one series output. The charges detected by the photosensors are received simultaneously by the two registers and transferred to a single read stage under the action of control voltages chosen so as to permit alternate reading of each register.

Abstract: A combined bipolar-field effect transistor RESURF device includes a lightly-doped epitaxial buried layer of a first conductivity type located between a semiconductor substrate of the first conductivity type and an epitaxial surface layer of a second conductivity type opposite to that of the first. The doping concentration and thickness of the epitaxial surface layer are selected in accordance with the Reduced Surface Field (RESURF) technique. A highly-doped buried region of the second conductivity type is located beneath the base region of the device and is sandwiched between the epitaxial buried layer and the epitaxial surface layer. The advantages of such a device include a substantially reduced "on" resistance, a more compact and flexible configuration, improved switching characteristics, reduced base device current requirements, and improved isolation.

Abstract: Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P type plug is used to connect the P collector of the PNP to the P base of the NPN in a region where the P base and P collector overlap. A single N epi-region serves as the base of the PNP and the collector of the NPN. The P plug is located within this N epi-region but part of the N epi-region adjacent to or around the P plug is left so that internal connection of the PNP base and NPN collector is not cut off by the P plug. The structure is particularly suited for use in large memory arrays. The method of fabrication is also described.

Abstract: Power semiconductor devices are manufactured using a flexible metal tape carrier to facilitate automation of the manufacturing process. Control leads are fashioned from portions of the tape carrier, with a main portion of the tape carrier serving as a main current lead. The manufacturing process permits thorough electrical testing of a power semiconductor chip prior to incorporation into a relatively expensive power device package. In particular, the power chip can be tested at full-rated current, at least where the current is pulsed at a low duty cycle.

Abstract: An output signal is derived from an output buffer to an external lead in a semiconductor device. In general, the output buffer is constructed using an MOS transistor and is located near a bonding pad on the chip. Therefore, the number of bonding pads which can be formed on the chip is limited by the output buffer space. The present invention provides the output buffer with a tapered or tiered shape which reduces the pitch between bonding pads. Thus, a large number of bonding pads (output buffers) can be integrated in a semiconductor chip according to the present invention.

Abstract: A semiconductor memory device including a first MIS transistor having source and drain regions formed in a substrate and a gate electrode provided on the substrate through an insulating layer; a semiconductor layer provided on the first MIS transistor through the insulating layer and being in contact with the source and drain regions of the first MIS transistor; a second MIS transistor having source and drain regions formed in the semiconductor layer and being in contact with the source and drain regions of the first MIS transistor and having a gate electrode provided on the semiconductor layer through an insulating layer; and a bit line being in contact with the source or drain region of the second MIS transistor and extended on the second MIS transistor; each gate electrode of the first and the second MIS transistors being connected with different word lines respectively, and impurities having an amount more than a required value being doped to at least one of the substrate and the semiconductor layer below

Abstract: The disclosure relates to a stepped insulator process for HgCdTe infared focal plane devices, the insulator being a combination of two insulator materials, ZnS and SiO, which differ in dielectric constant and chemical reactivity. The structure is patterned on HgCdTe which has an accumulated surface region. The resulting configuration significantly reduces pin hole short circuits introduced during via etching and improves the operating range (channel stopping action) for a given step height over that of ZnS alone.

Abstract: In accordance with the present invention, a plurality of strip-shaped emitter layers on the cathode side are radially arranged on one main surface of the semiconductor substrate while forming a plurality of rings. A gate electrode is in ohmic contact with a part of a base layer which surrounds and is adjacent to each of said emitter layers on the cathode side. Between rings formed by said emitter layers on the cathode side, a ring-shaped gate collecting electrode is provided to be connected to said gate electrode. The gate collecting electrode is provided at a position to balance the potential differences produced by gate currents respectively corresponding to inside and outside of said gate collecting electrode.

Abstract: Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region constituting current carrier recombination centers, form a layer with a peak concentration situated in proximity to the emitter-base junction of the inherent bipolar transistor. The layer of ions is of small thickness, whereby the resulting increase in the respective sheet resistances of the emitter and base layers to either side of the emitter-base junction is minimized.

Abstract: A focal plane array, comprised of an infrared (IR) photovoltaic detector array coupled to a charge coupled device (CCD), which provides for minimum deviation in input threshold voltage between individual detector input nodes of the array is disclosed. In one embodiment, an oxide nitride dielectric layer overlays the entire CCD with the exception of the areas beneath the direct injection gates where only a thin oxide dielectric is formed. In another embodiment, the oxide beneath the direct injection gates is substantially thinner than the oxide beneath the remainder of the CCD structure.

Abstract: This controlled electronic switching device for the suppression of transients can change over from a non-conductive state to a conductive state at lower triggering current levels than conventional devices while retaining unaltered its response characteristics to variations in the voltage applied thereacross. The device comprises a main switch which is triggered by a parallel-connected auxiliary switch having smaller junction areas and a higher capacitive current shunt resistance (resistance between base and emitter) than the main switch, thereby it turns on at lower control currents from the gate electrode for a given response to voltage variations.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.

Abstract: A parallel connected gate turn-off thyristor device including an additional short circuiting conductor connected between the gate terminals of the respective gate turn-off thyristors so as to bypass a part of the turn-on and turn-off gate currents of one gate turn-off thyristor to other gate turn-off thyristors to increase the turn-on and turn-off gate currents of the other gate turn-off thyristors thereby hastening the turn-on and turn-off operations of the other gate turn-off thyristors.

Abstract: A solid state image sensor is disclosed which includes a photosensitive region consisting of a group of first vertical shift registers formed of a plurality of charge transfer devices, light receiving areas, which are located between adjacent ones of the group of first vertical shift registers, electrically separated from one other by a channel stop region and capable of accumulating a charge, and read-out gate sections transferring signal charges of the light receiving areas to corresponding one of the first vertical shift registers, a storage section consisting of a group of second vertical shift registers electrically connected to one end of the vertical shift registers, a charge transfer horizontal shift register electrically connected to one end of the second vertical shift registers, and a section for field-reading out the signal charges in the photosensitive areas, the potentials of the read-out gate sections during the light receiving and accumulating period are selected to be different between the pe