Abstract: A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are disclosed. In this semiconductor integrated circuit device, a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wiring.

Abstract: A peripheral block of a semicustom integrated circuit comprises one input/output pad formed on a peripheral portion of a substrate and an N-channel MOS transistor formed in proximity of the input/output pad. A wiring conductor extends from the input/output pad to an internal circuit, and one the way, is connected to a drain region of the N-channel MOS transistor. A source and a gate of the N-channel MOS transistor is connected to a ground so as to function as a diode for protecting a large voltage inputted to the input/output pad, from the internal circuit.

Abstract: A Bi-CMOS semiconductor device includes a P-type semiconductor substrate, an N-type buried layer formed in the semiconductor substrate, a P-type well region formed on the buried layer, and an N-channel MOS transistor formed in a first predetermined area of the well region. The Bi-CMOS semiconductor device further includes an N-type surrounding layer formed to surround the well region in cooperation with the buried layer. The surrounding layer electrically isolates the well region from the substrate and the other P-type well region.

Abstract: A block of composite material includes a dielectric material with a dielectric constant of .epsilon..sub.d =4.66 and which is at least 4 .mu.m thick and has electrically conductive microparticles randomly distributed throughout. The composite material exhibits an optical bistability without cavity feedback. The microparticles must be nearly uniform in size and of spherical diameter much smaller than the wavelength of light in the particle. The composite, when illuminated by laser light in the range of 500 nm and of varying intensity, becomes opaque at a critical input intensity and stays opaque until the input intensity reaches a certain level both below and above the intensity at which it initially became opaque. Thus the material behaves as an optical switch and a limiter.

Abstract: An opaque shield is provided for integrated circuits and comprises reflective particles of titanium dioxide and light-absorbing particles of carbon black suspended in polyimide. The reflective particles increase the effective path length of light traversing the carrier so that a much lower concentration of carbon black is required to render the shield opaque. The concentration of carbon black can be low enough so that its conductivity does not impair operation of the integrated circuit. In addition to shielding the integrated circuit from light, the shield also protects the integrated circuit from contamination. A fluid precursor material is formed by mixing titanium dioxide and carbon black particles into a polyamic acid solution. This solution is diluted, filtered and vacuum distilled to yield a suspension free of over-sized particles. The resulting suspension can be applied and patterned using conventional semiconductor processing techniques.

Abstract: A semiconductor memory device having an improved capacitor configuration is provided in which storage node electrodes are formed projecting perpendicularly with respect to a substrate. Thus, the surface areas of the storage node electrodes are enlarged. As a result, memory cell chip areas can be minimized while maintaining the prescribed capacitance of storage capacitors. Further, a method of manufacturing the device is also provided.

Abstract: A semiconductor device in accordance with the present invention includes a semiconductor chip which is bonded to a die pad using a solder having a liquidus temperature of 370.degree. C. or less. A copper ball is moved to contact an Al electrode pad on the semiconductor chip in less than 150 ms after formation of the ball. Plastic deformation takes place so that the copper ball is pressed against the aluminum electrode pad and the height of the copper ball becomes 25 .mu.m or less. It is possible to firmly wire the Al pad on the semiconductor chip and the inner lead frame without cracking the glass coating by utilizing a silver plating on the die pad and an Au-metallized layer on the rear side of the semiconductor chip. It is also possible to decrease the work hardening property of the Cu ball and prevent Al exudation when the Cu ball is bonded to the Al electrode pad.

Abstract: A structure for an Integrated Injection Logic (I.sup.2 L) gate is disclosed in which gate gain .alpha.*.beta. is improved and leakage current at the silicon-silicon dioxide interface is reduced. A plug of highly doped material is interposed between the emitter and the collector of the lateral transistor to accomplish these goals.

Abstract: Element regions which are adjacent to each other in a channel width direction are displaced from each other in a channel length direction by 1/4 pitch. Cell plate electrodes are formed over the element regions through a capacitor insulation film to extend in an oblique direction. Groove portions formed in a step-form corresponding to the shape of the respective transistor forming regions of the element regions are each formed between corresponding two adjacent ones of the cell plate electrodes. Word lines are formed in a stripe configuration to extend in a channel width direction and used to directly apply potentials to the element regions. Contact holes are formed for contact hole opening preparation regions of the element regions. Bit lines are formed in a stripe configuration to extend in a length width direction and are connected to respective element regions (1) via the contact holes.

Abstract: A double heterojunction bipolar transistor which comprises a first conductivity type emitter layer, a second conductivity type base layer which is in contact with the emitter layer and forms a first heterojunction in conjunction with the emitter layer, and a collector layer which is in contact with the base layer and is made up of a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. The collector layer includes a low-impurity concentration layer which is in contact with the base layer. The low-impurity concentration layer has the same conductivity type as the base layer and has an impurity concentration lower than that of the base layer. The collector layer forms a second heterojunction in conjunction with the base layer. The emitter layer and the collector layer are formed of a semiconductor material having a band gap wider than that of the base layer.

Abstract: An arrangement for reducing piezo-electric effects in piezo-electric effect sensitive electrical components formed in a semiconductor body is disclosed. The piezo-electric effect sensitive component or components are located in a particular zone of the semiconductor body. The semiconductor body is in general mounted on a support. However, the zone of the semiconductor body containing the piezo-electric sensitive component or components is not attached to the support but instead is separated from the support by a space. The presence of the space results in a certain degree of mechanical isolation of the part of the semiconductor body which contains the piezo-electric effect sensitive components, whereby the negative influence of the piezo-electric effect on the long term stability of an instrument utilizing the semiconductor body is reduced.

Abstract: A driver circuit, which uses two serially connected enhancement mode n-channel MOS transistors in which the pullup transistor of the two transistors has no p-type implant in the channel region thereof and the pulldown transistor of the pair is a normlal enhancement mode transistor having a p-type threshold control implant in the channel thereof, is useful as a driver circuit for CMOS circiuts. The pullup transistor is designed to have a threshold of about 0 volts at zero back gate bias and the pulldown transistor is designed to have a threshold voltage of about 0.7 volts at zero back gate bias.