Abstract: There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.

Abstract: A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic.

Abstract: A modem and an improved phase-locked loop used in the modem. A presettable counter (251) generates the desired signal (TXCLKOUT). The reference input clock signal (TXCLKIN) and the generated clock signal (TXCLKOUT) are compared by an exclusive-OR gate (254). The output of the gate (254) is sampled by two flip-flops (256,266) before and after a rising edge of the TXCLKOUT signal. If the TXCLKIN and TXCLKOUT signals differ by more than a desired phase window a logic circuit (264) adjusts the preset inputs of the counter (251) so that the TXCLKIN and TXCLKOUT signals are in phase within the desired phase window.

Abstract: A control circuit for the switching of inductive loads which is monolithically integratable and includes an output stage having push-pull transistors. The base of each transistor of the output stage is connected to a driver circuit and to an auxiliary transistor which is biased in saturation. Each auxiliary transistor is driven to conduction in phase opposition with respect to the final transistor to which it is connected. The auxiliary transistor accelerates the turn-off of the final transistor, withdrawing the base charge, while delaying the turn-on thereof and absorbing the current fed thereto for a period of time equal to that of its own turn-off transient; in this way, the simultaneous conduction of the transistors of the final stage during the switching thereof can be avoided.

Abstract: A first 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency 8f.sub.SC of a signal. A second 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency of a signal obtained by inverting the signal of frequency 8f.sub.SC by an inverter. A first sampling pulse output circuit generates a first sampling pulse from an output signal from the first 5-stage ring counter. A second sampling pulse output circuit generates a second sampling pulse from an output signal from the second 5-stage ring counter. A phase correction circuit causes synchronization of the count operation of the first 5-stage ring counter with a clock run-in signal. This phase correction is performed by shifting the phase of the output from the first 5-stage ring counter in units of the period of the signal of frequency 8f.sub.SC.

Abstract: A phase comparator and data separator is disclosed capable of establishing a detection window of the order of 100 percent of the clock cycle at a data recovery rate at least as great as 100 MHz. One of the preferred embodiments of the invention comprises three bistable flip-flops interconnected with OR gates to respond to a data input pulse stream and a clock pulse stream to provide, in response to each data pulse, a reference pulse having a width equal to the bit cell period and a variable pulse having a duration which is greater or less than the reference pulse duration in accordance with the direction and amount of time displacement of the input pulse from the center of the bit cell in which the input pulse occurs.

Abstract: A circuit which eliminates race conditions caused by gate delay variation. In the absence of gate delay variations data is made available for a period of time which extends beyond commencement of processing of such data. This circuit prevents gate delay variations from causing processing to commence after the period of time during which data is available. Each of a pair of flip-flops initiates or terminates the data available time period. These flip-flops, an exclusive-or gate and related circuitry are arranged such that the period of time for data availability is not terminated until after processing of such data actually commences.

Abstract: A variable frequency passband circuit comprising two passband filters and three mixers (front, intermediate and output mixers) connected in a cascade fashion disposed in a signal path. Two VCOs inject frequency signals into the front mixer and the output mixer. The two VCOs are respectively controlled by control signals at two potentiometers through transfer switching means so that the synthetic passband of the filter may be varied. One potentiometer suppresses the higher frequency region of a baseband signal and the other potentiometer suppresses the lower frequency region of the base band signal, irrespective of USB or LSB receiving mode.