Patents Examined by R. W. Beausoliel, Jr.
  • Synchronizing a prediction RAM
    Patent number: 5649097
    Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: July 15, 1997
    Assignee: International Business Machines Corporation
    Inventors: Timothy B. Brodnax, Bryan K. Bullis, Steven A. King, Robert L. Schoenike, Daniel L. Stanley