Abstract: A multiphase interleaved forward power converter includes two or more subconverters and two or more subconverters clamping circuits. Each subconverter includes an input, an output, and a transformer coupled between the input and the output. The subconverters are phase shifted relative to each other such that a conduction period of one subconverter is at least partially complementary to an idle period of another subconverter. The clamping circuits each include a switching device coupled to at least one winding of the transformer of each subconverter. The clamping circuits each are configured to clamp a voltage across the at least one winding to substantially prevent a resonance voltage from propagating in the subconverters during their idle period. Additional example subconverters, clamping circuits, and methods for substantially preventing a resonance voltage from propagating in multiphase interleaved forward power converters are also disclosed.

Abstract: A system that provides intelligent constant on-time control may include a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch, the switching node configured to be connected to an inductor and a power output; feedback paths coupled to (1) a synthesized node and (2) the power output, the feedback paths enabling feedback of signals from (1) the synthesized node, and (2) the power output; and a controller coupled to the feedback paths. The controller may be configured to control a voltage at the power output based on a combination of the signals carried by the feedback paths.

Abstract: An active clamp switching power converter circuit includes a primary-side sensing circuit that generates a sensed voltage based on an auxiliary winding voltage of an auxiliary winding around the core having a same polarity as the primary winding. Based on the sensed voltage, a controller controls switching of a power switch coupled to the primary winding to control current through the primary winding and controls switching of an active clamp switch to control leakage current when the power switch is turned off. The controller regulates timing of the switching to turn on the power switch based on timing of a zero voltage switching condition for power efficient operation.

Abstract: An inverting apparatus comprises: a DC port; an AC port; five switches; a first capacitor coupled between the first terminal of the second switch and the second terminal of the fourth switch; and a free-wheeling element coupled between the second terminal of the third switch and the second terminal of the fifth switch; wherein the five switches are controlled so that the device can switch among a plurality of operating modes and transmit active or reactive power to a power grid.

Abstract: A method of the producing artificial gravity in an electromagnetized environment is provided with a bodysuit, a corridor, a plurality of mobile electromagnets, a plurality of mobile inertial measurement units (IMUs), a plurality of first fixed electromagnets, second fixed electromagnets, and at least one computing unit. The first fixed magnets and the second fixed magnets are integrated throughout the corridor to continuously generate a uniform magnetic field through the corridor. The mobile electromagnets are integrated throughout the bodysuit to electromagnetically interact with the first fixed electromagnets and the second fixed electromagnets, which simulates gravity as the bodysuit moves through the corridor. The mobile IMUs are integrated to the bodysuit so that the mobile IMUs sends spatial positioning and orientation data to the computing unit.

Abstract: A fault inrush transient current restraining type virtual synchronous inverter and thereof is disclosed. The invention solves the problem that a virtual synchronous inverter will be burned due to inrush transient current in an extreme situation of a symmetrical fault occurring on the grid side by setting an information collection module for inverter output voltages and currents, a virtual synchronous inverting control module, a fault detection and synthesize module, a hysteresis comparison control module and a post fault clearing switch back grid-tie control module.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: A voltage converter circuit comprises a charge pump circuit, a switching converter circuit, and a control circuit. The charge pump circuit includes multiple switch circuits connected in series. The switching converter circuit includes a first inductor coupled to an output node of the voltage converter circuit, and a second inductor coupled to a series connection of the multiple switch circuits. The control circuit is configured to control activation of the multiple switch circuits to generate a regulated voltage at the output node, and to activate each of the multiple switch circuits when a drain to source voltage of the switch circuit is zero volts.

Abstract: A power inversion apparatus includes a smoothing capacitor, first and second primary coils, a secondary coil, first to fourth switches of bridge circuit switches, a clamp capacitor, and a switch controller. The switch controller calculates a lower-arm duty ratio of each of the first and second switches using a map or a mathematical expression by feed-forward control based on an input voltage. The switch controller outputs a fixed value that is equal to or greater than a maximum value of the lower-arm duty ratio within a variation range of the input voltage as an upper-arm duty ratio of each of the third and fourth switches. The switch controller generates a pulse width modulation signal based on the calculated lower-arm duty ratio and the fixed value of the upper-arm duty ratio, and outputs the pulse width modulation signal to the bridge circuit switches.

Abstract: A vehicle includes a generator, an outlet, and a controller. The generator is electrically connected to the outlet. The controller is programmed to, responsive to outlet temperature being less than a threshold, deliver an electric current from the generator to an external device that is connected to the outlet. The controller is further programmed to, responsive to the outlet temperature exceeding the threshold, inhibit delivering the current from the electric machine to the external device.

Abstract: A switching power supply controller for a switching power supply is provided that measures an input voltage through an application of a load during an input voltage measurement period following connection of the switching power supply to an AC mains. Based upon the measured input voltage, the controller adjusts a start-up delay period so that the start-up delay period is substantially constant despite variations in an AC line voltage for the AC mains.

Abstract: A voltage balance control method applicable to a three-phase DC-AC inverter is provided, the voltage balance control method including: multiplying, by a first multiplier, an actual value of a line capacitance voltage by a sine function to generate a first voltage; capturing, by a first filter, a DC part of the first voltage to generate an error DC component; subtracting, by a first subtractor, the error DC component from a target voltage amplitude to generate a second voltage; adjusting, by a first proportional-integral controller, the second voltage to generate an amplitude error compensation value; and adding, by an adder, the amplitude error compensation value with the target voltage amplitude to generate an amplitude reference value. A voltage balance control device applicable to a three-phase DC-AC inverter is also provided.

Abstract: A power supply includes a transformer configured to transform a direct current (DC) voltage and supply an output voltage to a load. The power supply further includes circuitry configured to control the output voltage from the transformer, compare one of an average per unit time of the output voltage and an amplitude value of the output voltage with a threshold in a failure-free state when performing droop control of the output voltage, and determine whether a failure has occurred in at least one of the load and the transformer.

Abstract: A multi-port power supply apparatus and a power supplying method thereof are provided. The multi-port power supply apparatus includes a power supply circuit, a plurality of connecting ports, a plurality of power converters, and a common control circuit. The power supply circuit is configured to provide a source electric energy to the power converters. Any one of the power converters converts the source electric energy into an output electric energy and outputs the output electric energy to the corresponding connecting port. The common control circuit dynamically adjusts the source electric energy by controlling the power supply circuit according to a plurality of voltage demands and a plurality of power demands of the connecting ports, so as to enhance voltage conversion efficiency of the multi-port power supply apparatus.

Abstract: According to one aspect of the present disclosure, a single-stage converter includes a rectifying circuit and a buck-boost circuit. The buck-boost circuit includes an inductor with a center tap configured to supply an output of the buck-boost circuit to the rectifying circuit. The buck-boost circuit also includes first and second interleaved arms arranged in parallel with a voltage input of the single-stage converter. The first and second interleaved arms are each coupled to the inductor and include a plurality of switches operable to control the output of the buck-boost circuit.

Abstract: A hybrid circuit configuration, particularly a protection circuit configuration, includes: at least one first external conductor segment; a first mechanical bypass switch in the first external conductor segment; a first semiconductor switch configuration connected in parallel to the first bypass switch; a first electronic control unit for activating the first semiconductor switch configuration; and a bypass switch activation unit, to which bypass switch activation unit at least one field coil of the bypass switch is connected. At least one control terminal of the bypass switch activation unit is connected to the first electronic control unit. The electronic control unit and/or the bypass switch activation unit controls the at least one field coil of the bypass switch in a preconfigured way either with at least one first electric current or one second electric current, the one second electric current being greater than the at least one first electric current.

Abstract: In accordance with embodiments of the present disclosure, a system may include an impedance estimator configured to estimate an impedance of a load and generate a target current based at least on an input voltage and the impedance, a voltage feedback loop responsive to a difference between the input voltage and an output voltage of the load, and a current controller configured to, responsive to the voltage feedback loop, the impedance estimator, and the input voltage, generate an output current to the load.

Abstract: A tri-level converter provides three levels of power supply to a power amplifier that includes a supply path. The supply path has a first transistor and a first inherent body diode associated with the first transistor, as well as a second transistor and a second inherent body diode associated with the second transistor. A polarity of the second body diode is reversed relative to a polarity of the first body diode. A first driver is configured to drive the first transistor and the first inherent body diode to control a power supply, including a battery supply signal, to an output of the tri-level converter. The tri-level converter is coupled to a switching node.

Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the an input current drawn at an input of the power converter.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.