Abstract: An embodiment of an integrated circuit comprises circuitry to share page tables associated with a page between a processor memory management unit (MMU) and an input/output memory management unit (IOMMU), store a page table entry in the memory associated with the page, and separately control access to the page from a processor and from a direct memory access (DMA) request based on one or more fields of the stored page table entry. Other embodiments are disclosed and claimed.

Abstract: Selectively bypassing cache directory lookups for processing-in-memory instructions is described. In one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. A processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the memory address. The cache directory bypass bit for a processing-in-memory request controls whether a cache directory lookup is performed after the processing-in-memory request is issued by a processor core and before the processing-in-memory request is executed by a processing-in-memory component.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: A cache memory supports a plurality of insertion/promotion vectors (IPVs) and a replacement control circuit configured to update replacement data for the cache memory based on the plurality of IPVs. In one embodiment, the IPV is selected for a given request based a criticality status of a cache line accessed by the given request. For example, cache lines deemed important or critical for performance reasons may be replaced less frequently via a first IPV, while non-critical cache lines are replaced more frequently via a second IPV.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.

Abstract: In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.

Abstract: An I/O memory management unit operates to provide hardware moderated restrictions on access to internal I/O device addresses of I/O devices eliminating the interposition of the operating system in such data transfers. As well as providing read/write permissions, the I/O memory management unit can perform address translation for virtualization and may be the combined with the functions of an IOMMU for managing physical addresses.

Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: An illustrative method includes a storage-aware serverless function management system determining a status of a serverless system that implements one or more serverless functions configured to access one or more components of a storage system, determining a utilization of the storage system, and requesting that the storage system adjust storage of data in the storage system based on the status of the serverless system and the utilization of the storage system.

Abstract: A method, computer program product, and computing system for measuring a total storage controller throughput value for a workload processed on a storage controller within a storage array enclosure of a storage system. A maximum storage controller throughput value may be determined for the workload. A storage controller saturation value may be determined for the storage controller based upon, at least in part, the total storage controller throughput value for the workload and the maximum storage controller throughput value for the workload. One or more IO requests may be processed on one or more storage devices associated with the storage controller based upon, at least in part, the storage controller saturation value determined for the storage controller.

Abstract: Projecting capacity utilization for snapshots includes identifying one or more data release patterns of a storage system; identifying a snapshot policy; and generating, based on the one or more data release patterns and the snapshot policy, an estimate of an impact of the snapshot policy on a capacity of the storage system.

Abstract: Opportunistically transmitting backups through a time-limited air gap. A data protection system may predict rates of changes for one or more applications. The predicted rate of change allows a size of corresponding backups to be estimated. If there is time during which an air gap is available (closed), at least of the backups is selected and opportunistically transmitted to a vault through the air gap.

Abstract: Methods, systems, and apparatuses for storage device pool management based on storage device logical to physical (L2P) table information are provided. One such data storage system includes data storage devices each including a non-volatile memory; and a storage management device configured to receive L2P table information from at least two of the data storage devices; receive host data from a host device to be stored in one or more of the data storage devices; select, based on the L2P table information from the at plurality of data storage devices and the size of the host data, a target data storage device from the plurality of data storage devices; and send the host data to the target data storage device.

Abstract: Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QOS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

Abstract: A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.