Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

Abstract: A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.

Abstract: An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.

Abstract: There is provided a memory protection unit configured to maintain region metadata associated with storage regions of off-chip storage and protection metadata associated with each of the storage regions. The protection metadata is stored in the off-chip storage, and the region metadata encodes whether each of the storage regions belongs to a set of protected storage regions or to a set of unprotected storage regions and encodes information indicating corresponding protection metadata associated with each storage region. The memory protection unit is configured to update the region metadata in response to a region update request identifying a given storage region for which the region metadata is to be modified and to dynamically adjust an amount of memory required to store protection metadata associated with the set of protected storage regions in response to the update to the region metadata.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing non-RAM memory to implement a cloud storage system. An embodiment operates by receiving a request from an on-premises computer system to securely access a cloud drive by receiving an object specific template for an object. Based on the object specific template, an object specific plugin is selected, wherein the object specific plugin is configured to provide a connection to a cloud-based repository to obtain real time data for the object. An instance of the object is generated and communicated to a cloud plugin, wherein the cloud plugin is configured to communicate to a specific cloud drive through an HTTP client and further upload the instance of the object to the specific cloud drive.

Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Abstract: A method of dynamically adjusting workload of a data storage system includes, while processing a first workload, calculating a saturation value of a saturation metric that scales substantially linearly with an I/O per second (IOPS) rate relative to a maximum IOPS rate of the system, determining that the saturation value is one of (1) above a high threshold and (2) below a low threshold, and performing a workload adjustment operation that establishes a second workload by (1) subtracting from the first workload based on the saturation value being above the high threshold, and (2) adding to the first workload based on the saturation value being below the low threshold, then subsequently processing the second workload.

Abstract: Apparatuses, methods and techniques for controlling memory access in a data processing system are disclosed. The operating data processing system comprises multiple subsystems, each comprising at least one processing element and at least one peripheral device. Memory transaction control circuitry receives memory transaction information of a memory transaction comprising a stream identifier indicative of the issuing peripheral device. A main control register indicates an address of a stream table having multiple entries each comprising an owning subsystem identifier. At least one subsystem control register corresponding to each subsystem of the multiple subsystems stores memory access checking configuration information. On receipt of the memory transaction information an entry of the stream table is selected in dependence on the stream identifier. At least one subsystem control register. corresponding to the subsystem identified by the owning subsystem identifier of the entry is selected.

Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Abstract: A method of operating a storage device which communicates with a host device, includes receiving a request for an access to target data from the host device, executing an indirect access module based on the request, determining, by the indirect access module, a target address indicating a location of the target data based on an access parameter of the request, accessing, by the indirect access module, a data block based on the target address, and providing, by the indirect access module, the host device with the accessed data block or the target data in the accessed data block.

Abstract: An example computer-implemented method of controlling access to a storage system includes using, in response to a request to access a resource of the storage system during a transitional state associated with a transition of the storage system to use a security protocol to control access to the storage system, a guest role to control access to the resource of the storage system when the request does not include a token identifier

Abstract: A method, system, and device for writing compressed data to a disk, and a readable storage medium. The method includes: acquiring compressed data, and determining a length of the compressed data; storing the compressed data in a linked list, and adding the length of the compressed data to a linked list length, wherein the linked list length is a total length of all compressed data in the linked list; determining whether the linked list length exceeds a threshold value; and if YES, allocating an idle thread to merge all the compressed data in the linked list, and carrying out a write-to-disk operation on the merged compressed data.

Abstract: An aspect of the invention relates to a method of managing jobs in a information system (SI) on which a plurality of jobs run, the information system (SI) comprising a plurality of computer nodes (NDi) and at least a first storage tier (NS1) associated with a first performance tier and a second storage tier (NS2) associated with a second performance tier lower than the first performance tier, each job being associated with a priority level determined from a set of parameters comprising the node or nodes (NDi) on which the job is to be executed, the method comprising a step of scheduling the jobs as a function of the priority level associated with each job; the set of parameters used for determining the priority level also comprising a first parameter relating to the storage tier to be used for the data necessary for the execution of the job in question and a second parameter relating to the position of the data necessary for the execution of the job (TAi) in question.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages first account information to be used for authentication of a first account and second account information to be used for authentication of a second account. The controller receives third account information from a host device. When the third account information matches the first account information, the controller permits access to at least a partial storage area of the nonvolatile memory based on a request from the host device and transmits first data that includes the second account information to a first memory system.

Abstract: Disclosed is an electronic apparatus including a processor configured to obtain calculation information based on input data of a deconvolution calculation being input, obtain a size of output data based on the obtained calculation information, obtain a plurality of memory address values corresponding to a size of the output data using an address generation module, perform convolution calculation based on the calculation information using a convolution calculation module to obtain an intermediate value in the convolution calculation process, obtain a memory address value corresponding to the obtained intermediate value of the plurality of obtained memory addresses using the address generation module, store the obtained intermediate value in the memory address value corresponding to the intermediate value, accumulate at least one intermediate value based on the memory address value corresponding to the intermediate value using a cumulative calculation module, and obtain a deconvolution calculation value with re

Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

Abstract: In a data storage system that includes two or more storage engines in interconnected by a channel-based fabric, highly deduplicated data is identified and promoted to a dedupe performance tier characterized by mirrors on each of the storage engines. Blocks of deduplication data are scored based on reference counts and read-miss access patterns. Promotion of blocks to the dedupe performance tier and demotion of blocks from the dedupe performance tier are calculated based on the scores. Performance is enhanced by enabling highly deduplicated blocks to be accessed from engine-local memory and engine-local storage via switches rather than the channel-based fabric.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: A Logical Unit Number (LUN) division method and device includes checking and adjusting a connection manner and numbers of Serial Attached Small Computer System Interface (SCSI) (SAS) connections of storage enclosures and a controller, so as to make a maximum output bandwidth of each storage enclosure consistent (Si); querying controller port identifiers and storage enclosure identifiers (S2); creating a Mdisk array, and adding the corresponding controller port identifier and the corresponding storage enclosure identifier for each Mdisk (S3); logically dividing a storage space in the Mdisk array to create a volume, and dividing the volume into LUNs, whereby Mdisks that form the LUNs are made to come from different storage enclosures and different controller ports (S4); and mapping the LUNs to a host (S5).

Abstract: A device for detecting zone parallelity includes a detection control circuit configured to generate respective first and second requests for first and second zones among a plurality of zones included in a solid state drive (SSD). An SSD controller is configured to control the SSD by generating a first command and a second command corresponding to the first request and the second request, respectively, and to schedule the first command and the second command. The detection control circuit determines zone parallelity of the first and second zones using response characteristics of the responses of the SSD to the first request and the second request. The response characteristics may include a latency of a response.