Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: In a high density solid-state imaging device, of four charge transfer electrodes formed on a semiconductor substrate via a gate insulating film, a first electrode, a fourth electrode, and a part of a second electrode are made of a first conductive film, and a third electrode and the remaining portion of the second electrode are made of a second conductive film. In the second electrode, the first conductive film is joined to the second conductive film. An oxidation film formed by thermally oxidizing the first conductive film isolates the first electrode from the second electrode, the second electrode from the third electrode, and the third electrode from the fourth electrode. The end of the second conductive film is formed so as to locate on the oxidation film on the first conductive film.

Abstract: In semiconductor devices such as laser diodes (LD) and light emitting diodes (LED) based on gallium nitride thin films, low defect density is desired in the gallium nitride film. In the fabrication of such devices on a silicon carbide substrate surface, the gallium nitride film is formed on the silicon carbide substrate after the substrate surface is etched using hydrogen at an elevated temperature. In another embodiment, an aluminum nitride film is formed as a buffer layer between the gallium nitride film and the silicon carbide substrate, and, prior to aluminum nitride formation, the substrate surface is etched using hydrogen at an elevated temperature.

Abstract: A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region.