Abstract: A data signal is encoded as frequency modulation by selecting carrier sources of different phases in response to data signals and filtering the resultant wave to produce an output deviating from the carrier frequency for one signal time in response to a single shift of phase. A phasing switch stores a record of the last sent phase and a record of the parity value of the number of zeros sent. The selected phase is as last sent for a 0, advanced for a 1 when the zero parity is of one value, and retarded when the zero parity is of another value.

Abstract: The subband channels of a subband coder/decoder utilize different encoding/decoding algorithms so as to maximize overall signal transmission quality using a digital signal processor having limited digital memory capability. In the exemplary embodiment, a digitized 180-2900 Hz voice band signal is divided into four octave-spaced subbands. The highest frequency subband (1450-2900 Hz) is encoded/decoded using a block companded pulse code modulation (BCPCM) algorithm while each of the lower frequency subbands is encoded/decoded using an adaptive pulse code modulation (APCM) or an adaptive differential pulse code modulation (ADPCM) algorithm. The resulting "hybrid" vocoder tends to maximize the quality of transmitted voice signals while yet permitting implementation within constrained digitial memory capacity and/or constrained transmission channel bandwidth.

Abstract: A pulse signal processing circuit includes a NAND circuit that accepts periodic input pulses and an upper-limit detection signal from an upper limit detector and, when both an input pulse and the upper-limit detection signal are present, provides a setting signal to a flip-flop. When the flip-flop is set, it provides a discharging signal to activate a constant discharging current source. A capacitor is discharged by the discharging current source until the potential across the capacitor reaches a lower reference potential, when a lower-limit detection signal from a lower limit detector resets the flip-flop to terminate the discharging signal. The discharging signal also comprises the output pulse of the processing circuit. Resetting the flip-flop initiates a charging signal to activate a constant charging current source to charge the capacitor until it reaches an upper reference potential, when the upper-limit detection signal is provided to the NAND circuit to condition it to receive the next input pulse.

Abstract: A digital phase lock loop (PLL) circuit adaptable to a hard disk drive. The PLL operable at a high speed comprises a pulse shaper for subjecting raw data pulses from the disk drive to waveform-shaping, a phase comparator for producing a phase control pulse on the basis of the relative positions of a delayed reference clock (VCLK) pulse and each of said waveform-shaped data pulses from the shaper, and a phase shifter for generating the VCLK pulse in response to the phase control pulse.

Abstract: A communication system comprising a satellite, a master earth station (MES), and a plurality of small earth stations (SESs) provides signal transmissions addressed and transmittable to a selectable other SES via the satellite, the MES, and then the satellite again. The signal transmissions consist of bit representing pseudo random sequence (PRS) signals PRS.sub.SES which in turn consist of chips arranged in predetermined and identifiable patterns and with the bit and chip occurrence rates C.sub.SES and B.sub.SES of each SES being synchronized with each other as they arrive at the MES. The satellite responds to the signal transmissions from the SESs to retransmit the signal transmissions to the MES, which in turn responds to the signal transmissions from the satellite to amplify and retransmit such signal transmissions back to the satellite again. The satellite again responds to the signal transmissions from the MES to retransmit them to the SESs.

Abstract: Apparatus and a technique for equalizing non-linear distortion in a received modulated data signal by (1) forming tentative decisions as to the values of data symbols represented by the signal preferably using a receiver including a conventional linear equalizer, (2) constructing a replica of the non-linear distortion in response to the tentative decisions, and (3) forming a final decision as to the data symbol values in response to signals including the replica. If desired, the final decisions can also be stored and fed back to the processor which forms the replica, so that the replica is a joint function of past final decisions and future tentative decisions regarding the data symbols represented by the signal samples. The present invention provides increased accuracy by using tentative decisions rather than input samples to form the non-linear distortion replica.

Abstract: An improved driver for differentially driving a differentially conducting cable (e.g., for Ethernet) minimizes the output offset signal coupled to the cable when the driver is idle. When driven to an idle state, the driver provides a shaped output which transitions to a quiescent output level in a manner which eliminates output signal common mode step change and consequently reduces signal distortion on the cable due to reflection of the step change.

Abstract: The fading protection system protects against fading selectively occuring in a specific channel of a plural data transmission system. An equalizer is provided in each channel and adapted to equalize received data. An error correction mechanism is also provided for correcting errors of the received data in at least any one channel. A comparator associated with each channel is provided to deliver a first signal when the level of the received data in the associated channel has been reduced below a predetermined first threshold to indicate a level reduced channel. A controller operates in response to the first signal so as to deliver, as reference data, the correct data, after correction by the error correcting mechanism, to the equalizer provided in the level reduced channel.

Abstract: A circuit for reproducing a signal associated with synchronization with a digital data signal. The digital data signal includes a combination of a plurality of pulses each having a predetermined pulse width. The reproducing circuit comprises a logic circuit for discriminating the pulse width of at least one of the plurality of pulses, an oscillator and a frequency divider connected with the oscillator and responsive to the output of the logic circuit to generate a clock signal timed with the output of the logic circuit.

Abstract: Frame bit synchronizer for a framing pattern sequence consisting of M Bits distributed in a serial bit stream as single bits at intervals of a fixed number N, of bits, as measured from the start of one framing bit to the start of the next. The system initially operates in a framing mode, searching for frame, until the framing pattern sequence has been determined, upon which event the operation shifts to an in-frame monitoring mode for detecting errors in the framing pattern sequence in the serial bit stream as received.

Abstract: A radio data communications system is disclosed in which messages, normally lost to interference caused by independent remote units contending for the radio channel, may be salvaged. If a remote unit communicating a message to a fixed site is interrupted by a second remote unit having a stronger radio signal, the fixed site detects the increase of radio signal strength and activates a synchronization detector which responds to a synchronization data bit sequence which precedes each data message. If the synchronization sequence is detected, the remainder of the first remote data unit message is discarded and the message of the second remote data unit is processed.

Abstract: Pulse Code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code, characterized in that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law. The circuit forms part of a telephone line circuit (LC) connected between a telephone line (LI) and a digital switching network (SNW) and comprising the cascade connection of a subscriber line interface (SLIC) able to perform line control and supervision, a digital signal processor (DSP) mainly adapted to execute analog-to-digital and digital-to-analog conversion operations, the above transcoder circuit and a dual processor terminal controller (DPTC) which deals with the general control of the line circuit. The DSP only processes linear PCM signals, whereas the DPTC solely operates on companded PCM signals.

Abstract: A data transmission control system for allowing remote transceiver stations to transmit data via a telephone line or like analog transmission line through modems. When transmit and receive stations have been interconnected by a call, a training sequence for the modem is executed and, also, a test signal transmission sequence is effected to set up a data transmission rate before delivery of information. When the receive station has received test training data inclusive of a plurality of transmission rates from the transmit station, the function of the modem at the receive station is checked with respect to each of the transmission rates on a signal space diagram, thereby determining whether the receive station is capable of normally receiving data at the transmission rate. Training on the transmission rates which a modem can use is executed satisfying a predetermined protocol and without increasing the protocol time.

Abstract: A modem receiver having receiver control, signal detection, and data demodulation implemented with a single general-purpose integrated circuit microcomputer. Novel multirate digital signal processing techniques are included which provide complete real-time recovery of all data and modem signals in a microcomputer integrated circuit having an architecture not optimized for signal processing applications. The resulting techniques extend to more general signal processing applications which may be implemented by other general-purpose microcomputers, programmed signal processors, or specific dedicated hardware logic. The novel modem receiver includes digital FIR filters, performing quadrature signal detection, and post-demodulation data correction with an all-digital second-order carrier recovery loop.

Abstract: A method of transmitting binary data from one station to another via a troposcatter medium, characterized in that the data is converted to parallel form so that the bits produce distinctive pairs of sine and cosine harmonics having different frequencies, which harmonics are summed in two separated channels that are modulated by rf sine and cosine modulating signals that are combined and transmitted to the receiver, together with a test signal that was periodically inserted in the parallel bits. The receiver supplies the signals to banks of matched filters that produce a first set of signal estimates from which the test signal is detected. A matrix system responsive to the test signal produces from the first set of estimates a second set of signal estimates having lower distortion than the first set.

Abstract: A timing recovery circuit for synchronous data transmission using a signal which, in the baseband, is formed by a succession of two-level signal elements, without overlap, and of duration T, able to take one of the four forms defined by the functions: ##EQU1## comprises a transition selection circuit. This circuit selects transitions in the received signal, in the baseband, separated from those which immediately precede them by a time-delay situated in an arbitrary range. This range brackets a symbol duration of between 3/4 and 5/4 times, exclusive, the duration of a signal element. A timebase which is synchronized on the transitions selected by the selection circuit delivers the signal element recovered timing.

Abstract: An on-the-fly data compression system for compressing the data transmitted between a data source and an ultimate utilization device. The system normally has two data compression modules implementing a conventional multi-buffering scheme and a decoder for reconstructing the compressed data to its original format. The data compression modules compresses the data using a word representation by associative processing buffer and a content induced transaction overlap transmission protocol which results in an interleaved transmission of data bits and bit position bits, the latter being indicative of the number of data bits that will be transmitted during the subsequent data transmission. The decoder reconstructs the compressed data to its original format in response to the transmitted data and bit position bits and stores them in a pair of buffers in the sequential order in which they were generated.

Abstract: The present invention relates to a modem that allows the user to switch back and forth between voice and data telecommunications during the same phone call without redialing. Such switching back and forth between voice and data telecommunications is accomplished by lifting the telephone handset for voice communications and replacing the telephone handset for resumption of data communications. The present invention also allows a local user to communicate with a remote user via a speaker at the remote modem location without the remote user picking up the remote handset.

Abstract: The data communication system includes an encoder to receive nonreturn-to-zero data signals and convert them to biphase signals, a current mode transmitter for transmitting the biphase signals, and a communication link connected to the transmitter. The encoder senses transitions in the nonreturn-to-zero data signals and controls the amplitude of the biphase signals in response to the sensed transitions. These transitions are sensed by inverting and delaying the nonreturn-to-zero data signals and exclusively ORing these delayed and inverted signals with the nonreturn-to-zero data signals.

Abstract: An adaptive equalizer arrangement for digital transmission system comprises at the output of the transmission channel a first in-phase path and in parallel with this first path, a second quadrature path, both paths being of the non-recursive transversal filter type having n branches and (n-1) delay circuits between the inputs of these branches, each of these n branches comprising, arranged in series, a mixer, a low-pass filter, a multiplier, and having their outputs connected to an adder which is followed by a sampling circuit and thereafter by a comparator circuit to decide the symbols to be transmitted from the outputs of these paths. The arrangement also comprises a third control path which comprises two subtracting circuits to determine the differences between the signals before and after decision and a control circuit of a voltage-controlled oscillator, 2n phase shifters and 2n multipliers.