Abstract: A method of achieving consistent cache coherence control in a tightly coupled multi-processor system with a plurality of processors having copy-back cache memories and a shared memory connected by a split transfer system bus. In this method, the cache memory data management is accomplished by using cache memory states for labelling each data entry in the cache memories, the cache memory states including at least one transient state for awaiting data transfer after a corresponding address transfer, and access is prohibited to data which is in the transient state in one cache memory by a processor other that the processor associated with this one cache memory.