Abstract: An audio rate converter converts a sampling rate for audio data into a fixed rate. In the audio rate converter, an input audio data DAin at a sampling rate of PFS (48 kHz.+-.x%) are stored in the memory in accordance with a write address WAD which is synchronized with the rate PFS. Audio data are read from the memory in accordance with a read address RAD which is synchronized with a rate FS (48 kHz), and coefficient data determined based on a sampling point in output audio data are read from a ROM table in accordance with a read address Coef.AD which is synchronized with the rate FS. A data arithmetic and logic circuit performs multiplying and adding operations using these data in order to produce the output audio data DAout. If the sampling rate PFS at which the input audio data are provided changes, the audio rate converter can provide the output audio data DAout at the fixed sampling rate FS.

Abstract: An apparatus for real time 2-D IDCT comprises a rate buffer, a pair of multiplexers, a plurality of registers, a plurality of parameter extractors, a plurality of accumulators, a plurality of summing elements, a pair of truncators, a transpose buffer and an inverse rate buffer. In the present invention, data input rate of the rate buffer and output rate of the inverse rate buffer are a first rate, while the transform process, which is carried out between the rate buffer and the inverse rate buffer, is at a second rate. Moreover, a distributed arithmetic structure is utilized in the invention to decrease the circuit complexity and increase the operating efficiency. Therefore, real time 2-D IDCT can be achieved by the apparatus of the present invention.

Abstract: The automatic registration control system of the present invention is a closed loop system including a driving mechanism for feeding a continuous web of disposable absorbent articles, such as diaper pads, toward a cutter. The cutter may separate completed pads from the web. A sensor is positioned along the manufacturing line, and preferably preceding the cutter, for detecting at least one preselected feature of each diaper pad and producing a detection signal when the feature passes by the sensor. A position resolver determines the angular position of the cutter at the moment when the preselected diaper feature is detected, and the average angular position is calculated from a predetermined number of cutter positions. The average cutter position is compared to and subtracted from a target cutter position to produce an error signal. The error signal is then converted into a control signal and supplied to a phase variator which adjusts the position of the cutter in response to the control signal.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication.

Abstract: In a system for storing same data in first and second storages, a central controller for producing a duplex write control signal on a bus. An I/O processor processes the duplex write control signal received from the bus into first and second write control signals to deliver the first and the second write control signals to first and second DMA controllers connected to the first and the second storages. A request controller selects, as a first selected request, that one of first and second data transfer requests simultaneously produced by the first and the second DMA controllers in response to the first and the second write control signals. Supposing that the first selected request is the first data transfer request, a data buffer controller controls the first DMA controller in response to the first selected request to read the data from a main memory on the bus and to write the data in the first storage. Simultaneously, the data buffer controller makes a data buffer memory memorize the data.