Abstract: A multiprocessor system architecture in which two processors are each provided with an autonomous bus and the two buses can be selectively connected to each other to form a unique system bus which enables access by all processors to common memory resources connected to one of the autonomous buses. The communication between processors takes place through messages stored into mailboxes located in the common memory. The presence of a message is evidenced by a notify/interrupt signal generated by a logic unit to which each processor has access to modify and verify the logic unit's status, using the processor's autonomous bus, and without interfering with operations using the other autonomous buses of the other processor. Such verification and access does not require access to common memory resources nor polling operations to verify the status of messages stored into "mailboxes".

Abstract: An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes.The virtual machine makes all hardware devices appear to be processes, in that the occurrence of an event on a device causes a message to be generated and sent to another process for handling. The receiving process performs all operations required to handle the event. Thus a variety of hardware devices can be connected and disconnected from the system without interrupting its operation and without necessitating extensive software revisions.

Abstract: A plurality of operation units are connected to one another. The operation units include a processor, a buffer memory, and a data transfer control circuit connected between the processor and the buffer memory for controlling the data input-output with the buffer memories in the other of the operation units. The buffer memories and the data transfer control circuit are connected with one another by data buses, respectively.

Abstract: A multiple-hierarchical-level multiprocessor system having first numbers of processing modules comprising, each, at least one processor and connected to a first group of common direct-access communication lines for forming a first hierarchical level (family); a first processing module of each of the aforementioned first numbers also being connected to a second group of common direct-access communication lines for forming a second hierarchical level (region); a second number of the aforementioned second groups of common communication lines being interconnected via data transmitting and receiving means for forming a third hierarcical level (region network); the aforementioned means comprising at least one processor for enabling operation independent of the aforementioned modules.

Abstract: Chemical structure data containing generic representation of component atoms in a storage device is searched by finding a match between a query structure and a stored candidate structure by mathematically comparing attribute data of chemical units of a query structure and attribute data of chemical unit of a stored candidate structure, where attribute data represent chemical characteristics of chemical units of those structures.

Abstract: A microcomputer system including an EPROM (electrically programmable read-only memory) which can be programmed either externally or by the control processing unit of the system. The control means, normally responsive to externally applied control signals, is disabled by a register of the system which can be set by the control processing unit and by an address decoder connected to the address bus.

Abstract: In many situations, contiguous data is not stored at contiguous locations within a memory. This fact alone causes an increase in processor time for retrieval purposes or the intervention of a memory management unit of some type. The situation is compounded when large amounts of data must be obtained from the memory or stored in the memory in real time. This problem is addressed by arranging a dual ported memory between the main memory and the processor and transferring the desired data into the dual ported memory. A pair of buffers are then used for each channel having access to the memory. While one buffer is being read, the other is being loaded. This structure also allows multiple devices to access the single main memory substantially simultaneously.

Abstract: A content addressable memory for storing data words wherein each data word includes one or more characters is disclosed. One or more of the characters stored in said content addressable memory may be retrieved in response to commands from a controller coupled to the content addressable memory. The controller includes command circuitry for generating and coupling a plurality of control signals to the content addressable memory, including control signals defining a specification character. The controller also contains response circuitry for receiving a plurality of response signals from the content addressable memory. These response signals include signals specifying a character stored in the content addressable memory. The content addressable memory is constructed from a plurality of storage sections. Each storage section includes control bus coupling circuitry for coupling that storage section to the controller and to the other storage sections.

Abstract: Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in first predetermined states; a set flag operation places both elements in second predetermined states; a read flag operation alters the state of the second storage element; and a clear flag alters the state of the first storage element if and only if the state of the second storage element has previously been altered by a read flag operation. The flag output corresponds to the state of the first storage element. When implemented with single instructions, inadvertant flag negation and errors due to intervening interrupts are avoided. The read flag operation temporarily disables the set flag mechanism, protecting against setting the flag during a read operation. The flag is always read as asserted prior to being negated.

Abstract: A cache memory control apparatus according to the present invention includes data register blocks which are individually controlled for each byte, cache memory blocks, and a decoder for generating control signals which control the access to those blocks. In this cache memory control apparatus, when a cache hit is made in a write mode for byte data, the control signal is supplied to the data register blocks and cache memory blocks to individually control the respective blocks, thereby allowing word data corresponding to the write byte data to be synthesized. Thus, the word data can be output to an external device by one operation.

Abstract: A microprocessor system debug tool has a mainframe which interfaces with a user. A ROM emulator replaces a ROM unit of the microprocessor system to be tested and has a monitor portion which is used to perform debug functions specified by the user. A user defined control line is connected to the interrupt system of the microprocessor system to cause the target microprocessor to stop execution of the user's program and jump to the monitor portion upon the occurrence of a user defined event to execute microprocessor specific debug code generated by the mainframe in response to the user's input. At the conclusion of debug code execution the microprocessor resumes the user's program. A word recognizer is connected to the microprocessor bus to detect the results of the debug code execution, the results being forwarded to the mainframe for display to the user.

Abstract: A financial system includes a plurality of peripherals like a magnetic stripe reader, printer, and keyboard which are coupled to a personal computer by an adapter board which is inserted into an interface bus within the computer. Even though the financial application being run may be single tasking, the system is capable of running multi-tasking operations. An encryptor/decryptor processor, which is used in handling secure data, is located on the adapter board to minimize unauthorized access to the secure data.

Abstract: A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal.

Abstract: A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory address), a plurality of processors connected in parallel, the processors each having means for initiating an access of data from any of the memory elements simultaneously with accesses of other processors, the memory elements each being capable of accepting an access from just one of the processors during a given cycle, and the memory elements being interleaved so that the memory access patterns generated at a stride of one and a stride of two each meet the conditions that (1) the pattern will tolerate being offset with respect to an identical pattern by a desired offset and any multiple of the offset (wherein tolerating means that no memory access conflicts arise, i.e.

Abstract: This invention pertains to database management systems and, in particular, to a database management system which has an active data dictionary that the user can both access and modify. The user makes use of simple commands to control, order and query not only the underlying data controlled by the database management system but also the contents of the data dictionary. This capability enables the user to write generic application programs which are logically independent of the data since the subject database management system enables the user/application program to access all data in the database independent of each application program's data model.

Abstract: A data processing terminal device is on-line connected to a host computer and records on journal paper journal data obtained as a result of communication with the host computer. Data is encrypted, and encrypted data is exchanged between the terminal device and the host computer. The encrypted journal data received by the terminal is decrypted and printed on a journal paper, then modified and stored in a PROM. By comparing the journal data with the modified data, journal data alteration can be easily detected.

Abstract: A device is provided for supplying microprocessors with electricity, comprising a source for supplying with power microprocessors interconnected by a bus. The source has an initialization output connected directly to a bus so that the microprocessors do not execute their programs during the rise in voltage. Each microprocessor comprises an initialization counter also connected to the bus for recognizing the initialization signal of the source. Each microprocessor also comprises its own initialization generator adapted for detecting an absence of traffic on the bus and for emitting an initialization signal over the bus in the case of "unbuckling" of one of the microprocessors.

Abstract: A microprogram controlled data processing apparatus is described, in which each machine-level instruction is divided into a number of phases, and each phase is executed by a sequence of microinstructions. The machine-level instruction is decoded to produce a set of microprogram parameters, and in each phase of the instruction a sub-set of these parameters is selected, and broadcast over a parameter bus to individual decoders which decode the microinstructions, so as to qualify the effects of the microinstructions. The use of parameters in this way allows the same microprogram sequence to be used for several different instruction variants, and hence reduces the total size of the microprogram.

Abstract: The system comprises a central processing unit which processes received data, a memory unit which stores programs required for the operations of this central processing unit and other data, a data transmission adapter which receives the data, an output control unit which delivers the received data to each output end under the control of said central processing unit, and a mode setting unit which stores output mode data for setting an output mode at each output end when the received data are abnormal. When the received data are abnormal, the output mode data and the output data outputted already to the output control unit are taken in, said output data are modified into those in an output mode designated by the output mode data, and the output data thus modified are delivered to the output control unit.