Patents Examined by Reginald G. Bragoon
  • Patent number: 5890212
    Abstract: A method of managing commands is provided for a disk drive having an intelligent interface for communicating with a host. The drive also has a magnetic disk, host side programs, disk side programs, and a cache wherein the cache is divisible into a number of segments. The cache employs a cache control structure including a cache entry table, a buffer counter, a block count, a host pointer and a disk pointer. The drive receives a first command and a second command with a cache access type. The method of managing commands comprises the steps of: processing the first command to assign the first command to a cache segment having a prefetch area; determining the cache access type of the second command; and if the cache access type of the second command is a skip ahead sequential access then decrementing the buffer counter and incrementing the host pointer to skip leading nonrequested data in the prefetch area for the first command.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: March 30, 1999
    Assignee: Western Digital Corporation
    Inventors: Daniel John Sokolov, Timothy W. Swatosh
  • Patent number: 5806083
    Abstract: A content addressable memory comprising a random access memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entry as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment the RAM comprises an array of n RAMs, wherein the at least a portion of a data entity is segmented into n slices.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: September 8, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Ron Edgar