Abstract: A method for operating a disk storage system, comprising a disk and forming part of a communications network, simultaneously maintains the continuity of a plurality of data streams. Typically, each stream transfers video data to or from the disk storage system. Illustratively, each of the data streams is produced in the network at a rate of W.sub.base bits/sec and consumed by the disk storage system or produced by said disk storage system and consumed in the network at a rate of W.sub.base bits/sec. One I/O transaction is performed for each stream in each of a plurality of I/O cycles of duration S/W.sub.base, wherein in each I/O transaction a segment of S bits is retrieved from or stored in the disk. The number of streams whose continuity can be maintained in this manner is limited by the number of I/O's which can be performed in a cycle of duration S/W.sub.base. More generally, when a stream has a bit rate (A/B)W.sub.

Abstract: An object-oriented input/output (IO) system represents an interface between clients of the IO system and peripheral devices, such that the clients can access the peripheral devices by utilizing IO services offered by the IO system. The IO system includes one or more object-oriented IO servicers for receiving IO service requests from clients, and for generating IO commands in accordance with the IO service requests. One or more object-oriented access managers, coupled to the IO servicers and the peripheral devices, access the peripheral devices as instructed by the IO commands such that the IO service requests are satisfied. The peripheral devices may transmit interrupts to a kernel while operating in accordance with the IO commands. One or more object-oriented interrupt servicers, coupled to the kernel receive and decode the interrupts from the peripheral devices. One or more object-oriented interrupt handlers, coupled to the interrupt servicers, process the decoded interrupts.

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle.

Abstract: A rendering system for processing rendering command packets includes a plurality of prefetch circuits which are supplied with a rendering command packet including a rendering command and a parameter and prefetch a next rendering command packet during processing of the former rendering command packet, and a plurality of primitive creating circuits coupled in parallel, each of the primitive creating circuits being coupled to associated one of the prefetch circuits to start processing the next rendering command packet when completing the processing of the former rendering command packet.

Abstract: An apparatus which allows for software sharing between multiple controllers includes a computer bus and a plurality of processors each having input and output ports coupled to the bus. Each processor also has at least one internal storage register. The apparatus further includes means, which are responsive to a signal indicating which one of the plurality of processors is controlling the computer bus and to a portion of address data on the bus, for issuing a control signal to one of the plurality of processors to permit that one processor access to at least one of its internal storage register when that processor issues a bus access request having an address which is within the range of addresses of all the processors.