Abstract: A digital phase-locked loop for speed measurement, in particular for use in antiskid control systems, for the conversion of the frequency of an input pulse sequence, proportional to a speed, into a digital numerical value to be used in the digital arithmetic unit for an antiskid control system is provided wherein there is a certain numerical value which will always be the same which is allocated to any input pulse sequence and which can be applied to a first storage register and added to the contents therein. At regular intervals, determined by a clock generator, a positive digital output numerical value is generated by a detector if the content of the first storage register is above a predetermined upper limit and a negative digital output numerical value will be generated if the contents of the first storage register are below a predetermined lower limit.