Abstract: An interposer includes a substrate, first and second sets of contact pads carried by the substrate, and receptacles formed in a surface of the substrate and exposing contact pads of the second set. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles are configured to at least partially receive conductive structures, such as solder balls, that are secured to the contact pads of the second set. Thus, the interposer is useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages. In addition, methods for designing and fabricating the interposer are disclosed, as are methods for forming assemblies, packages, and multi-chip modules that include the interposer.

Abstract: An optoelectronic package (10) includes a base substrate (40), a plurality of solder pads (21) and a can (30). The base substrate includes a mounting seat (41) laminated first and second layer (421,422). The solder pads (21) respectively attach to a top surface (412) and a bottom surface (4212) of the base substrate and are electrically interconnected with each other via conductive material filled the through-holes (411,4223,4213) and conductor trace (45,45?). Optoelectronic components (not shown) are attached to the top surface of the base substrate and make electrical connection with the solder pads. The can includes a transparent device (31), an metal enclosure (32) and a housing (33), which hermetically seals to the base substrate protecting the optoelectronic components.

Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Abstract: A semiconductor-producing/examining device that can maintain a preferable connection state for a predetermined period of time and that can easily remove a ceramic substrate from a supporting case. The semiconductor producing/examining device includes a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof and a supporting case. An external terminal is connected to the conductor layer. A connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.

Abstract: A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

Abstract: Light emitting devices with improved light extraction efficiency are provided. The light emitting devices have a stack of layers including semiconductor layers comprising an active region. The stack is bonded to a transparent optical element having a refractive index for light emitted by the active region preferably greater than about 1.5, more preferably greater than about 1.8. A method of bonding a transparent optical element (e.g., a lens or an optical concentrator) to a light emitting device comprising an active region includes elevating a temperature of the optical element and the stack and applying a pressure to press the optical element and the light emitting device together. A block of optical element material may be bonded to the light emitting device and then shaped into an optical element. Bonding a high refractive index optical element to a light emitting device improves the light extraction efficiency of the light emitting device by reducing loss due to total internal reflection.

Abstract: This invention describes an approach for monolithically integrating all the components of a photoreceiver—optical amplifier, optical band-pass filter, and photodiode module—on a single chip. The photoreceiver array employs unique optical amplifier and conversion technologies that provides the ultra-sensitivity required for free space optical communications networks. As an example, by monolithically integrating a vertical cavity surface emitting laser-diode (VCSEL) optical preamplifier with a photodiode receiver and related amplifiers and filters on the same chip, sensitivities as low as ?47 dBm (62 photons/bit at 2.5 Gb/s), along with an order of magnitude reduction in size, weight, and power consumption over comparable commercial-off-the-shelf (COTS) components can be demonstrated.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.

Abstract: In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

Abstract: An optoelectronic component with an epitaxial semiconductor layer sequence having an active zone that emits electromagnetic radiation, and at least one electrical contact region having at least one radiation-transmissive electrical contact layer, which contains ZnO and is electrically conductively connected to an outer semiconductor layer. The contact layer is provided with watertight material in such a way that it is substantially protected against moisture.

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.

Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Abstract: A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed between third and fourth semiconductor regions. The method comprises the steps of, in turn, halo-implanting each of the first, second, third, and fourth semiconductor regions, with the other three semiconductor regions being masked, in a projected direction which (i) is essentially perpendicular to the direction of the respective gate region and (ii) points from the halo-implanted semiconductor region to the respective gate region.

Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.

Abstract: In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate should have different second impurity region lengths, respectively, according to difference of the operating voltages.

Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract: The present invention provides a solid-state rotational rate sensor device formed by a thin-film for generating an electrical voltage output proportional to the rate of rotational motion. The precision thin-film piezoelectric elements are configured and arranged on a semi-rigid structure to detect rotation (such as pitch, roll, and yaw) while rejecting spurious noise created by vibration, thermal gradients, and electro-magnetic interference.