Patents Examined by Remmon R Fordé
  • Highly reflective ohmic contacts to III-nitride flip-chip LEDs
    Patent number: 6573537
    Abstract: An inverted III-nitride light-emitting device (LED) with highly reflective ohmic contacts includes n- and p-electrode metallizations that are opaque, highly reflective, and provide excellent current spreading. The n- and p-electrodes each absorb less than 25% of incident light per pass at the peak emission wavelength of the LED active region.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: June 3, 2003
    Assignee: Lumileds Lighting, U.S., LLC
    Inventors: Daniel A. Steigerwald, Steven D. Lester, Jonathan J. Wierer, Jr.
  • Heterojunction bipolar transistor with silicon-germanium base
    Patent number: 6573539
    Abstract: A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventor: Feng-Yi Huang
  • Capacitance element
    Patent number: 6573588
    Abstract: A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: June 3, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshio Kumamoto, Takashi Okuda, Yasuo Morimoto
  • Cells array of mask read only memory
    Patent number: 6570235
    Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: May 27, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Chun-Jung Lin
  • Optoelectric integrated device having a three-dimensional solid configuration
    Patent number: 6563137
    Abstract: An optoelectric integrated device includes a three-dimensional solid semiconductor crystal, such as a silicon ball, and a plurality of optical devices including a light-emitting device and a light-receiving device integrated on the surface of the semiconductor crystal. Light is emitted and received between the light-emitting device and the light-receiving device through the interior of the semiconductor crystal used as an optical wiring medium.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: May 13, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mamoru Uchida
  • Process for growing epitaxial gallium nitride and composite wafers
    Patent number: 6563144
    Abstract: A novel growth procedure to grow epitaxial Group III metal nitride thin films on lattice-mismatched substrates is proposed. Demonstrated are the quality improvement of epitaxial GaN layers using a pure metallic Ga buffer layer on c-plane sapphire substrate. X-ray rocking curve results indicate that the layers had excellent structural properties. The electron Hall mobility increases to an outstandingly high value of &mgr;>400 cm2/Vs for an electron background concentration of 4×1017 cm−3.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: May 13, 2003
    Assignee: The Regents of the University of California
    Inventors: Eicke R. Weber, Sudhir G. Subramanya, Yihwan Kim, Joachim Kruger
  • Monolithic series/parallel led arrays formed on highly resistive substrates
    Patent number: 6547249
    Abstract: Series or parallel LED arrays are formed on a highly resistive substrate, such that both the p- and n-contacts for the array are on the same side of the array. The individual LEDs are electrically isolated from each other by trenches or by ion implantation. Interconnects deposited on the array connects the contacts of the individual LEDs in the array. In some embodiments, the LEDs are III-nitride devices formed on sapphire substrates. In one embodiment, two LEDs formed on a single substrate are connected in antiparallel to form a monolithic electrostatic discharge protection circuit. In one embodiment, multiple LEDs formed on a single substrate are connected in series . In one embodiment, multiple LEDs formed on a single substrate are connected in parallel. In some embodiments, a layer of phosphor covers a portion of the substrate on which one or more individual LEDs is formed.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: April 15, 2003
    Assignee: Lumileds Lighting U.S., LLC
    Inventors: William David Collins, III, Jerome Chandra Bhat, Daniel Alexander Steigerwald
  • Color-optimized pixel array design
    Patent number: 6548833
    Abstract: A color optimized CMOS photodiode pixel array is provided. The pixel array employs different dimensions to take advantage of different characteristics of the photodiode physics to produce an enhanced image while minimizing the need for post processing. The design includes a relatively shallow blue pixel photodiode, a deeper green pixel photodiode, and a relatively deep red pixel photodiode. The red pixel photodiode is larger and deeper than the green pixel photodiode, which is larger and deeper than the blue pixel photodiode. Each color pixel photodiode comprises a junction diode and a depletion region. The CMOS construction of the three color pixel photodiodes may vary, but one possible construct of the red pixel photodiode would be an N Well/P Sub diode construct, the green pixel photodiode a N+/P Sub diode construct, and the blue being a N+/P Well or N+/P Sub diode construct.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 15, 2003
    Assignee: Biomorphic VLSI, Inc.
    Inventors: Chi-Shao Sergi Lin, Bimal P. Mathur, Taichi Wang
  • Semiconductor device
    Patent number: 6548884
    Abstract: A semiconductor device having a fuse evaluation circuit is provided. Fuse evaluation circuit (100) can include, a reference voltage generation circuit (110), a fuse circuit (120-n), and a fuse evaluation control circuit (130). Fuse circuit (120-n) can include a fuse (Fn) and evaluation transistor (Tn) arranged in-series and providing an evaluation node (Nn) at their connection. Reference voltage generation circuit (110) can provide a reference voltage (VG1) at a control gate of evaluation transistor (Tn). Fuse evaluation control circuit (130) can vary the impedance of the evaluation transistor (Tn) by varying the potential of reference voltage (VG1). Fuse evaluation circuit (100) can evaluate the condition of fuse (Fn) accordingly.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: April 15, 2003
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventor: Takeshi Oikawa
  • Thin film transistor-liquid crystal display and manufacturing method thereof
    Patent number: 6545292
    Abstract: This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: April 8, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Gyu Kim
  • Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof
    Patent number: 6545317
    Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Hokazono, Mariko Takayanagi
  • Precision high-frequency capacitor formed on semiconductor substrate
    Patent number: 6538300
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: March 25, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • High Q inductor with faraday shield and dielectric well buried in substrate
    Patent number: 6534843
    Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.
    Type: Grant
    Filed: February 10, 2001
    Date of Patent: March 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Raul E. Acosta, Jennifer L. Lund, Robert A. Groves, Joanna Rosner, Steven A. Cordes, Melanie L. Carasso
  • Semiconductor device and manufacturing method thereof for realizing high packaging density
    Patent number: 6531755
    Abstract: In a semiconductor device in which an interlayer insulating layer is formed of a low density material (porous silica etc.) and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased in comparison with other parts of the interlayer insulating layer. The densification process is conducted by the elimination of microvoids near the processed surface, for example. The densification or the microvoid elimination can be conducted by use of ammonia water, vapor of ammonia water, ammonia plasma treatment, etc. By the densification process, coating of the electrically conductive material (Cu etc.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: March 11, 2003
    Assignee: NEC Corporation
    Inventor: Tatsuya Usami
  • Chip size image sensor bumped package
    Patent number: 6528857
    Abstract: An image sensor package includes an image sensor having an upper surface. The image sensor further includes an active area and bond pads on the upper surface. A window is supported above the active area by a window support. Interior traces are formed on a lower surface of a step up ring. Electrically conductive bumps are formed between the interior traces on the lower surface of the step up ring and the bond pads on the upper surface of the image sensor thus flip chip mounting the step up ring to the image sensor. Electrically conductive vias extend through the step up ring to electrically connect the interior traces to exterior traces formed on an upper surface of the step up ring.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: March 4, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Steven Webster, Markus K. Liebhard
  • MSM device and method of manufacturing same
    Patent number: 6528827
    Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 4, 2003
    Assignee: OptoLynx, Inc.
    Inventor: Jason P. Henning
  • Foil wound low profile L-C power processor
    Patent number: 6528859
    Abstract: The present invention provides a foil wound low profile power L-C processor. A magnetic winding is disposed within a core. The magnetic winding can be made of one or more sets of conductive foil and insulation film wound together in a spiral pattern. The magnetic winding can also include dielectric film. The magnetic winding can have a center aperture in which a non-magnetic and non-conductive center post can be disposed. The center post can also be divided into portions with a combined length less than the length of the center aperture to form an air gap within the center aperture.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: March 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Willem G. Odendaal
  • Semiconductor device for integrated injection logic cell and process for fabricating the same
    Patent number: 6525401
    Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: February 25, 2003
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • IR sensor and method for fabricating the same
    Patent number: 6518597
    Abstract: Infrared ray sensor and method for fabricating the same, the method including the steps of (a) forming a diaphragm on a substrate, (b) forming and patterning a semiconductor film on the diaphragm to form a first thermoelectric material film, and forming and patterning a conductor film on the diaphragm, to form a metal resistance layer in a region of the first thermoelectric material film and a second thermoelectric material film in a region of the diaphragm, (c) forming a protection film on an entire surface inclusive of the metal resistance layer, (d) forming a black body on the protection film, and (e) removing a back side portion of the substrate, to expose the diaphragm, whereby maintaining a high sensitivity, requiring no additional process, reducing Jhonson noise, and improving yield.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: February 11, 2003
    Assignee: LG Electronics Inc.
    Inventor: In Sik Kim
  • Light-emitting device with organic layer doped with photoluminescent material
    Patent number: 6515314
    Abstract: A light-emitting device includes an anode, a cathode, and at least one organic electroluminescent (“EL”) material positioned between the anode and the cathode. Nanoparticles of at least one photoluminescent material are dispersed in the organic EL material. The organic EL material emits a first electromagnetic (“EM”) radiation having a first spectrum in response to an applied electrical field. The PL material absorbs a portion of the first EM radiation emitted by the organic EL material and emits a second EM radiation having a second spectrum. A plurality of the light-emitting devices are arranged on a transparent substrate to provide a panel display or a lighting source.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: February 4, 2003
    Assignee: General Electric Company
    Inventors: Anil Raj Duggal, Alok Mani Srivastava, Steven Jude Duclos