Abstract: The method is intended for obtaining nanosize amorphous particles, which find use in various fields of science and technology; in particular, metallic nanostructures can be regarded as a promising material for creating new sensors and electronic and optoelectronic devices and for developing new types of highly selective solid catalysts. The method for obtaining nanoparticles includes the following stages: dispersion of a molten material; supply of the resulting liquid drops of this material into a plasma with parameters satisfying the aforementioned relationships, which is formed in an inert gas at a pressure of 10?414 10?1 Pa; cooling of liquid nanoparticles formed in the said plasma to their hardening; and deposition of the resulting solid nanoparticles onto a support.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filed with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract: A method of glass frit bonding wafers to form a package, in which the width of the glass bond line between the wafers is minimized to reduce package size. The method entails the use of a glass frit material containing a particulate filler material that establishes the stand-off distance between wafers, instead of relying on discrete structural features on one of the wafers dedicated to this function. In addition, the amount of glass frit material used to form the glass bond line between wafers is reduced to such levels as to reduce the width of the glass bond line, allowing the overall size of the package to be minimized. To accommodate the variability associated with screening processes when low volume lines of paste are printed, the invention further entails the use of storage regions defined by walls adjacent the glass bond line to accommodate excess glass frit material without significantly increasing the width of the bond line.

Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein a residual organic compound layer on the surface of a substrate is used to facilitate removal of unwanted encapsulant material. An organic compound layer which inherently forms on the substrate during the fabrication of the substrate or during various chip attachment processes is masked in a predetermined location with a mask. The substrate is then cleaned to remove the organic compound layer. The mask protects the masked portion of the organic material layer which becomes a release layer to facilitate gate break. An encapsulant mold is placed over the substrate and chip and an encapsulant material is injected into the encapsulant mold cavity through an interconnection channel. The release layer is formed in a position to reside as the bottom of the interconnection channel. Preferably, the interconnection channel has a gate adjacent the encapsulant mold cavity.

Abstract: The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: Processing of applying ultraviolet rays to a front face of an insulating film material formed on a wafer W is performed, whereby a contact angle of the front face thereof becomes smaller. Accordingly, when an insulating film material is applied on the aforesaid front face, the material smoothly spreads, and projections and depressions never occur on a front face of an upper layer insulating film material. Thereby, it is possible to form the insulating film thick and flatter on a substrate.

Abstract: A process for maintaining a semiconductor substrate layer (e.g. a TiN, W or TEOS) deposition equipment chamber in a preconditioned and low particulate state between successive layer depositions. The first step is determining that the equipment chamber has been in an idle state for more than a first predetermined time period. In the second step, the equipment chamber pressure is reduced to its base pressure in the absence of gas flow, while maintaining the equipment chamber at a first predetermined temperature. In the third step, the equipment chamber is maintained at a second predetermined temperature for a second predetermined time period. During this step, the equipment chamber pressure is held at a first predetermined pressure, while an inert gas is discharged at a first predetermined inert gas flow rate through the equipment chamber. The pressure, time period and gas flow rate in this step are selected in such a way that adequate and thorough heating (i.e.

Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Abstract: A process of preparing tritiated porous silicon in which porous silicon is equilibrated with a gaseous vapor containing HT/T.sub.2 gas in a diluent for a time sufficient for tritium in the gas phase to replace hydrogen present in the pore surfaces of the porous silicon.