Abstract: Electronic assemblies, especially one containing volatile memory, used a flexible membrane with conducting lines which acts as an intrusion sensor against chemical and mechanical attacks. The lines are fabricated from inherently conducting polymers which are solution processed and directly patterned. The material was applied to a flexible polymer film by spin coating and patterned by application of a resist, followed by exposure/development of the resist and transferring the image into the polyaniline by reactive ion etching techniques. The conducting lines have high conductivity, tranparency properties which made them difficult to detect and possess excellent adhesion to the substrate film, as well as to the potting material which enclosed the structure. They also offered lightweight advantages over conventionally filled materials. These materials can also be used in conjunction with conventional conductor materials to further enhance protection against intrusion by sophisticated mechanical means.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.

Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.

Abstract: The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).

Abstract: A method of forming a floating structure lifting up from a substrate and a method of manufacturing a field emission device (FED) employing the floating structure are provided. The method of forming a floating structure includes forming an expansion causer layer, which can generate a byproduct from the reacting with a predetermined reactant gas causing volume expansion, on the substrate; forming an object material layer for the floating structure on a resultant stack; forming a hole through which the reactant gas is supplied on a resultant stack; supplying the reactant gas through the hole so that the object material layer partially lifts up from the substrate due to the byproduct generated from the reaction of the expansion causer layer with the reactant gas; and removing the byproduct through the hole so that the portion of the object material layer lifting up from the substrate can be completely separated from the substrate to form the floating structure.

Abstract: A membrane structure comprising a silicon film having a grain structure including grains defining pores therebetween.

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.

Abstract: A solder metal made of a eutectic or stoichiometric composition including at least two metallic or semiconducting elements is applied to a contact (of the semiconductor component, brought into contact with the metal layer of a metallized film and alloyed by heating into the metal layer of the film, thereby producing an electrically conductive connection having a higher melting point. A solder metal that is particularly suitable for such a purpose is the Bi22In78 (melting point 73° C.), Bi43Sn57, or In52Sn48, or BiIn, or BiIn2.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a programmable material is formed on the adhesive and on the electrode. In an aspect, a method is provided such that an adhesive is formed on a dielectric, an opening is formed through the dielectric exposing a contact formed on a substrate, and a programmable material is formed on the adhesive and on a portion of the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240).

Abstract: An LCD panel is provided, the LCD panel having a substrate, a conductive layer positioned on the substrate, and a dielectric layer disposed on the surface of the conductive layer. First, a photoresist layer with an opening is formed on the dielectric layer. An etching process is then performed to form a contact hole along the opening. After that, a post treatment process is performed to form a protective layer to reduce damage on the conductive layer when the photoresist layer is stripped.

Abstract: An integrated circuit is formed by a method having the steps of providing a circuit substrate with a first metallized region, providing a first insulation layer covered by a silicon layer, patterning the first insulation layer and silicon layer to form a first insulation region and first silicon region, then forming a second metallized layer on the silicon region, heating the material so that the second metal layer diffuses into the silicon layer to form a metal silicide region, which is subsequently covered by a second insulating layer having a contact with an interconnect to enable contacting an antifuse formed by the metal silicide region.

Abstract: The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.

Abstract: A WN film serving as an adhesive layer is deposited over the sidewalls and bottom surface of a hole in a silicon oxide film where an information storage capacitor is to be formed. A Ru film to serve as a lower electrode for the information storage capacitor is formed above the WN film by CVD using Ru(HFAC)3, H2O and H2 as ingredients, so that a ratio of partial pressure of H2O to H2 is controlled to be in the area below a curve (a). When the Ru film is formed by CVD utilizing hydrolysis, the film quality of the Ru film can be enhanced. The ratio of partial pressure of H2O to H2 is controlled, whereby oxidation of the Ru film can be suppressed. When it is controlled to be in the area below a curve (b) to form the Ru film, oxidation of the WN film can be suppressed.

Abstract: A semiconductor package is comprised of a semiconductor device 4 mounted on a die-pad 3, a wire 6 for electrically connecting some electrodes of the semiconductor device 4 and terminals 5 of lead frame, wires 8 for bonding the other electrodes of semiconductor device to the surface of die-pad for grounding, and molding compound 7 for encapsulating the outer area of semiconductor device 4 under a state where the back face of die-pad 3. The lower face and side face of terminals 5 are exposed, wherein portions plated with silver for connecting of wires on the surface of the die-pad are formed at points positioned between a peripheral edge of the die-pad and an outer edge of the semiconductor device while leaving spaces from both the edges. The adhesion of die-pad 3 to bonding compound 7 is improved to avoid the occurrence of wires coming-off even if heat is applied to the contact points of die-pad 3 to wires 8 when mounting semiconductor package on a printed circuit board.

Abstract: A methodology is described by which a processing chamber used to deposit plasma-enhanced Ti-CVD films may be conditioned and passivated efficiently after either a wet cleaning or in-situ chemical cleaning, or after each successive deposition sequence. The technique allows a CVD process, such as, for example, a Ti-PECVD process, to recover film properties, such as resistivity, uniformity, and deposition rate, in a minimum time and following a minimum number of conditioning wafers, thereby improving the productivity of the system. The technique also maintains the stability of the system during continuous operation. This allows for the processing of thousands of wafers between in-situ cleaning of the chamber.