Patents Examined by Rey Potter
  • Damascene structure at semiconductor substrate level
    Patent number: 7049702
    Abstract: A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: May 23, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Horng-Huei Tseng