Patents Examined by Richarad Booth
  • Patent number: 6133099
    Abstract: A vertical MOSFET of the present invention comprises a semiconductor wafer having a groove selectively etching in the semiconductor wafer to have substantially vertical side walls. The groove is oxidized using local oxidation of silicon (LOCOS) at 1100.degree. C. or greater to form a LOCOS film on the semiconductor wafer in the groove so that a whole side surface of said semiconductor wafer exposed by the groove is substantially vertical and essentially flat. The LOCOS film in the groove is removed and a thermal insulating film on the semiconductor wafer in the groove. Then a gate electrode made of a conductive film is formed on the thermal insulating film. An interlayer insulating film is formed on the gate electrode and a source electrode is formed in ohmic contact with a source region and a base region. A drain electrode is connected to the opposite side of the semiconductor wafer.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: October 17, 2000
    Assignee: NEC Corporation
    Inventor: Masami Sawada