Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

Abstract: An apparatus for providing storage is provided that includes a jitter buffer element. The jitter buffer element includes a primary jitter buffer storage that includes a primary low water mark and a primary high water mark. The jitter buffer element also includes a secondary jitter buffer storage that includes a secondary low water mark and a secondary high water mark. A first data segment within the primary jitter buffer storage is held for a processor. A playout point may advance from a bottom of the primary jitter buffer storage to the primary low water mark. When the playout point reaches the primary low water mark, the processor communicates a message for the secondary jitter buffer storage to request a second data segment up to the secondary high water mark associated with the secondary jitter buffer storage.

Abstract: Method for decreasing the existence of externally detectable revealing signals, so-called {umlaut over (R)}Ö{umlaut over (S)}, from keyboards (1), e.g. for computers, where the keyboard is fed with signals, so-called matrix signals, which are detected for detection of activity regarding the keys (2) of the keyboard, whereby said matrix signals are generated by means of signal devices. The method is especially characterized in that the matrix signals are high-frequency filtered before they are fed to the keyboard.

Abstract: A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.

Abstract: A buffer accessible by an application executing under an application server in a first address space is managed by a database adapter executing in a second address space. A data request from the application executing in said first address space, comprising a buffer locator in the empty state, is received by the database adapter executing in the second address space. A buffer is allocated in the first address space and the address of this buffer is stored in the buffer locator. Data associated with the data request, received from a database subsystem, is copied to the buffer. Control is then transferred back to the application whereby the application utilizes the buffer locator to access the buffer and process the data contained therein. A database adapter automatically managing application buffers across address spaces in accordance with the present invention may be referred to as an “auto-buffer database adapter”.

Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information. For example, it may be determined at a requesting agent processor that IO traffic is to be received at the target processor cache, wherein the target processor is different than the requesting agent processor. Moreover, routing information associated with the IO traffic may be received from the requesting agent processor. It may then be arranged for the IO traffic to be transferred directly into the target processor cache in accordance with the routine information.

Abstract: A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.

Abstract: In a device and method for controlling packet flow, priority data of a packet received by one of a plurality of ports are determined. A packet memory is monitored to determine whether an address pointer of the packet memory exceeds a predetermined limit value. A port is selected to control packet flow by using the priority data when the address pointer of the packet memory exceeds the predetermined limit value. Then, the selected port is directed to control the packet flow. By using the priority data designated to a packet or a port, the packet flow may be controlled in consideration of various kinds of network services.

Abstract: The present invention proposes a device for controlling a stream of data packets, comprising: a buffer (2) adapted to receive a data packet stream from a data source (1) and to output said packet data stream with an output rate to a packet data communication network (7), a monitoring means (4) adapted to monitor a fill level of said buffer (2), a detection means (5) adapted to detect a fill level condition of said buffer (2), in which an incoming data packet has to be dropped, and adapted to control a dropping means (6) for dropping an incoming data packet upon detection of said fill level condition, and further comprising an output rate control means (5a, 8, 9, 10, 11) adapted to control an output rate adjusting means (3) which is adapted to adjust said output rate of said buffer (2), wherein said output rate control means, in response to said fill level condition detected by said detection means (5), issues a first control signal (5a) controlling said adjusting means (3) to increase a current output rate of

Abstract: An initiating subsystem transfers a data set either in or out in subsets such as packets. Packet transfer is sequential, and transfer of a packet is contingent upon successful transfer of a previous packet. Actual data transfer to or from a destination, over a channel, is handled by a host interface. When an intermediate subsystem, included as an interface between the initiating subsystem and host interface, senses that the initiating subsystem wants to transfer data, it receives a first packet from the initiating system. While continuing to indicate to the initiating system that transfer of the first packet is still pending, thereby causing the initiating system to suspend further packet submission, the intermediate subsystem sends to the host interface information concerning the entire data set to be transferred. When the entire data set is transferred, the intermediate subsystem emulates successful packet-wise transfer to the initiating subsystem.

Abstract: The processor of a receiving device does not execute acquisition and release of resources of a band and a channel for the isochronous data transfer every time the processor receives data from the sending device by isochronous transfer, but executes the acquisition of the resources of the band and the channel for the isochronous data transfer via the bus and an I/F board only when the completion of a bus reset is detected and holds the resources until the next bus reset is caused. By this processing, the receiving device can consistently secure the resources necessary for the isochronous data transfer to the sending device so long as the resources acquisition is successfully achieved when the bus reset is completed.

Abstract: In the case where a rewind or fast-forward button is clicked after a playback button is clicked, a CPU on controller side sets a reproduction flag bit to “on” upon receipt of a response frame from a DV camcorder indicating that the playback command is normally accepted, without checking whether the DV camcorder is during playback operation or not, and determines what kind of control command should be sent to the DV camcorder based on the reproduction flag bit and the clicked button. The controller can determine the control command without waiting for the response to an inquiry about whether the DV camcorder is during playback operation or not, thus quickly sending a rewind playback or fast-forward playback command to the DV camcorder.