Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Abstract: Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: The invention provides an apparatus and method for performing a process on a substrate. At least two types of structures may be used to provide a flow path for a substrate so that the substrate may be moved from one processing or loading position to another. The first is a conveyor. The second is a track. The flow path may be a closed continuous loop. Each processing island has a valve for introduction and extraction of the substrate into and out of an interior of the island. The processing island may include load locks, and may include in conjunction therewith an inspection station, a CVD chamber, a PECVD chamber, a PVD chamber, a post-anneal chamber, a cleaning chamber, a descumming chamber, an etch chamber, or a combination of such chambers.

Abstract: Integrated circuit memory devices include a column select signal generator which generates a column select signal (CSL) having leading and trailing edges and a preferred timing controller. The timing controller, which is electrically coupled to the column select signal generator and is responsive to at least one latency state signal (e.g., CLy), adjusts the timing of at least one of the leading and trailing edges of the column select signal pulse as a function of the value of the at least one latency state signal. Here, the value of the latency state signal can be adjusted to cause a shift in the timing of the column select signal (CSL) and thereby reduce the likelihood of reading errors. In particular, the timing controller is responsive to a first internal clock signal (e.g., PCLK) and generates first and second control signals as CSLE and CSLD. The column select signal generator is responsive to the first and second control signals.