Abstract: A memory test system of the present invention comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. The common memory unit has an interrupt controller (INT CNT) 22. In each of the memory test units 90, a slave processor (MCPU) 40 and a memory for the slave processor (MEM) 14 are provided. MCPU 40 reads memory test results and responses of local processors (RCPU) 42 to 46 which are stored in RMEMs 32 and transfers read data to SMEM 16. MCPU 40 generates an interrupt signal. When all MCPUs 40 generate interrupt signals, INT CNT 22 generates an interrupt signal INT to the EWS 10. The EWS 10 may perform several functions based on the interrupt signal INT.

Abstract: An internal clock signal, of which a pulse repetition period is half of that of an external clock signal, is produced in a test circuit from the external clock signal and an external clock enabling signal of which a phase is shifted from that of the external clock signal by ¼ of the pulse repetition period of the external clock signal. When an external write command signal set to a low level is received in the test circuit, an internal write command signal, of which a level is risen up in synchronization with a leading edge of the external clock signal, is produced, and a first pre-charge signal, of which a level is risen up in synchronization with a trailing edge of the internal clock signal obtained just after the leading edge of the external clock signal, is produced. Therefore a write recovery time-period equal to ¼ of the pulse repetition period of the external clock signal is obtained from the internal write command signal and the first pre-charge signal.

Abstract: A highly reliable industrial control system is produced by opening multiple connections on a connected messaging network running a standard serial protocol. The two connections are used to transmit redundant data and include a reply message to the message producer. Errors in the messages or media failure may be detected using standard error detection codes, retry counters and deadman timers. Comparison of the data of the two messages can reveal other types of failure not apparent by these former techniques.

Abstract: A command from a host computer is held in a command holding section, and commands set in a register are referenced to determine whether or not the held command involves data transfer. If the command involves data transfer, a switching signal output section outputs switching identifying signals SX and SY to a command switching section. Thus, the command involves data transfer, control is provided by a hardware configuration without using a CPU. Alternatively, when the command involves no data transfer, the switching signal output section outputs an interrupt to the CPU. The CPU interprets the command held in the command holding section to output the switching identifying signals SX and SY to the command switching section.

Abstract: A method of recovering lost frames transmitted between a packet data sending unit and a packet data receiving unit in a data communications system is disclosed. When a frame is successfully received by the packet data receiving unit, it identifies a failure to successfully receive prior frames, i.e., at least one frame prior to the frame successfully received at the packet data receiving unit. The packet data receiving unit starts a selective reject wait timer and determines whether the number of frames missed so far is greater than or equal to a predetermined threshold. If the number of missed frames is greater than or equal to the preset limit, the packet data receiving unit generates a selective reject message that includes a payload indicating a first missed frame and subsequent missed frames.

Abstract: A computer network remote data mirroring system writes update data both to a local data device and to a local, chronologically sequenced journal storage area, or writelog device. A graphical user interface enables a user to create and configure throttles, which are user-defined tests and actions evaluated by the primary mirror daemon to regulate network bandwidth, CPU, and writelog device utilization during data update mirroring. Network bandwidth throttling enables a predetermined portion of the network bandwidth to be assigned to remote data mirroring based on user-selected criteria. CPU throttling enables a user to control the amount of time the local data storage unit will wait prior to returning control to applications after an update. Writelog device throttling prevents a memory overflow condition by dynamically assigning memory to the writelog device by chaining writelog device extensions to the writelog device.

Abstract: A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for replacing normal units. The semiconductor memory has a selection circuit for selecting one of the redundant units. A non-volatile first memory unit for storing an address, which can be programmed by an energy beam, of a normal unit to be replaced is provided. A non-volatile second memory unit for storing an address, which can be programmed via electrical contact is also provided. The first and second memory units are connected to the selection circuit for transmitting their respective stored information to the selection circuit. A repair can thus be carried out on the unhoused semiconductor memory and on the housed semiconductor memory. Since only a sufficient portion of all the redundant circuits to be provided are configured in such a way, this allows a space requirement that is smaller overall.

Abstract: A system for stressing and monitoring an electrical device, such that the imposed stress conditions may be terminated at electronic speeds, thereby preventing destruction of the device under test. The system includes stress channels each paired with a control and monitor circuit, such that the control and monitor circuit may shut down the stress if a limiting stress level is detected by the control and monitor circuit. A microprocessor is used to communicate via a digital control bus with each of the paired stress channels and control and monitor circuits to determine the status of the stress channel; control the stress input; and enable or disable the control and monitor circuits. A computer is used to communicate with the microprocessor through a serial interface.

Abstract: A fault handling monitor transparently using multiple technologies for fault handling in a shared system resource, such as a network file server, providing services to clients communicating with the system resource through a network. The system resource is organized as a cluster of multiple hierarchical and peer domains wherein each domain includes domain centered fault handling mechanisms operating cooperatively across domains. The system resource includes a network domain including a plurality of client/resource communications paths and supporting client/resource communications between the system resource and clients of the system resource, a resource service domain performing low level resource services operations, and a control/processing domain supporting the client/resource communications of the network domain, performing high level resource service operations and providing communications for resource service operations between the network domain and the resource service domain.

Abstract: A high level transaction logging mechanism for use in a shared system resource, such as a file server, and a high level, cross server transaction mirror logging mechanism. A system resource includes first and second blade processors, each including a first processor transforming high level operations into corresponding low level operations and a transaction logging mechanism including a log generator for extracting high level operation information relating to each system resource request and a transaction log for storing the high level operation information. The logging mechanism is responsive to restoration of operation of the system resource for reading the high level operation information from the transaction log and restoring the state of execution of the first processor.

Abstract: A method, system and computer program are described for isolating bus errors detected during system start-up by utilizing a technique in which a shared mailbox associated with a service processor is provided for holding the address of an adapter in an I/O drawer. If an error is detected the server processor is notified. The server processor then retrieves the address from the mailbox, uses it to derive a location code which is then passed along with the error code to an appropriate error analysis routine. The start-up procedure is then shut down.

Abstract: A monitoring system allows users to monitor the performance of a web-based or other transactional server. The system includes an agent component (“agent”) which simulates the actions of actual users of the transactional server while monitoring the server's performance. The agent may run on agent computers at a variety of locations. Using a controller component of the system, a user can preferably select a group of agent computers to include in a monitoring session, and assign transactions and execution schedules to such computers. Performance data collected from the agent computers is displayed by a web-based reports server that provides features for viewing the data as seen by agent computers having specific attributes or attribute sets. The system also includes features for capturing and displaying screens returned by the transactional server on failed transactions, and for measuring and reporting segment delays between an agent computer and the transactional server.

Abstract: An apparatus for and method of automatically generating, transmitting, receiving, and verifying test request messages within a large scale resource sharing computer system. In the preferred mode, the testing technique is applied to a memory resource having up to four requester ports. The test messages are simultaneously but randomly generated within each of the requester ports. These test messages are transferred to the memory resource. The responses from the memory resource are automatically verified within each of the receiving requester ports.

Abstract: A method for recording events in Java. According to a preferred embodiment, an automator is attached to a Java applet. Responsive to selection by a user, listeners are added for each event type produced in the Java applet. Each time a specified event occurs, that event is captured and saved to a data structure. The recording of events is performed until the user stops the process.

Abstract: A network device receives signals transmitted via a network and generates trigger messages. The network device transmits the trigger messages to an intelligent network platform that performs a network control function. The network device and the intelligent network platform both include redundant systems to provide increased reliability and rerouting capabilities in case one or more of the components experiences problems or a failure.

Abstract: A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.

Abstract: A method and apparatus for providing feedback to a programmer of a web based application notifying the programmer of application errors encountered by an end user of the application. A user error table is created to log application errors when a user computer is running the web based application. The present invention searches the user error table to determine whether an application error has occurred and only those errors which occur for a first time are forwarded to a server responsible for collecting the programmer's e-mail. A server error table is created to log those error messages received by the server and only those error messages which are unique are forwarded to the programmer. The programmer does not receive duplicate error messages relating to the same error and can use the feedback provided by the present invention to correct the application in subsequent versions.

Abstract: A bus extender for extending synchronous busses of limited length provides convenient access to bus cards in ATE systems. The bus extender plugs into a synchronous bus, for example, a PCI bus, and a cable carries bus signals to a remote location, where a remote card is engaged. The bus extender supports both initiator (master) and target (slave) modes of the remote card, and communicates with the remote card in the native protocol of the bus. The bus extender operates without requiring separate control from the bus. For example, the bus extender does not require its own device driver. The bus extender includes a bus snooper circuit that monitors bus transactions with the remote card and stores configuration data. The bus snooper circuit responds locally on behalf of the remote card to bus requests that require rapid responses. The bus extender further includes a state machine that copies the stored configuration data to the remote card to reset the remote card without requiring a reset of the bus.

Abstract: The present invention discloses a fault indicator circuit in a system having a plurality of circuit blocks each provided with an individual power source. Each of the circuit blocks needs to indicate a fault when a fault occurs in the individual power source of the circuit block. The fault indicator circuit of the present invention includes a fault indicator which performs fault indication in response to a fault indication control signal from the circuit block having the fault or one of the other circuit blocks. When a fault occurs in the individual power source of a circuit block, the fault indicator performs fault indication by means of power supplied from the individual power source of one of the other circuit blocks. An input determiner which reduces the level of the fault indicator control signal outputted from one of the other circuit blocks is disposed at the input terminal of a gate circuit into which the fault indication control signal is inputted from one of the other circuit blocks.

Abstract: A method and apparatus for ensuring the coherence of multiple copies of the same data at multiple geographic locations is presented. The system operating system, the system operator or some combination of both may determine the physical disks having the file or comprising the disk families containing data which requires protection. Using the MIRROR CREATE commands in a Unisys MCP operating system environment, a mirrored disk pack set is made for each relevant physical disk identified. The disk pack set is distributed amongst at least two geographic locations. For each member of each disk pack set, the STORESAFE+command associates a site identifier with the member corresponding to the member's geographic location. During application processing, disk writes for one member of a mirrored set are performed for each member of the set. The MCP operating system checks the results of each disk write to each of the members of the mirrored disk set.