Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

Abstract: A thermally stable inter-metal dielectric for interlayer dielectric material has enhanced adhesiveness by introduction of an adhesive material. The adhesive material may reside only at the interface of the inter-metal dielectric or interlayer dielectric with adjacent metalization and polysilicon layers. A disclosed thermally stable intermetal dielectric is a fluorinated polymer such as polyfluoropyreline. A disclosed adhesive material is a highly polar material such as a thiofluorocarbon. These materials may be deposited by chemical vapor deposition by first activating fluoropyreline monomer and di(thiodifluoromethane) in a heated activation chamber to convert them to a form suitably reactive to form a polymeric dielectric on a wafer surface.