Abstract: A support assembly for mounting a semiconductor device vertically relative to a carrier substrate. The support assembly includes an interposer to which the semiconductor device is attached. The support assembly also includes traces carried on the interposer, which electronically connect the semiconductor device to contacts on the interposer. The contacts are disposed along a single edge of the interposer. The invention also includes an alignment device for releaseably mounting the support assembly. The alignment device, which mounts to a carrier substrate, includes one or more receptacles. As a support assembly is inserted into a receptacle, the alignment device establishes an electrical connection between the contacts and corresponding terminals on the carrier substrate. The assembly may also include a cover that attaches to the top of the alignment device and biases the interposer against the carrier substrate.

Abstract: The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. A gate is first formed in a predetermined area on the surface of the semiconductor wafer. A first ion implantation process is then performed to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD). A uniform and oxygen-free dielectric layer is formed on the surface of the semiconductor wafer that covers the gate. A spacer is formed on each wall of the gate. Finally, a second ion implantation process is performed to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.

Abstract: In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.

Abstract: A second coat film is formed on a first coat film containing a conductive substance, the second coat film having an expansion coefficient almost the same as the expansion coefficient of the first coat film under a sintering condition. The first and second coat films are sintered at the same time. Thus, a conductive anti-reflection film with sufficiently low surface resistance, excellent water resistance and chemical resistance, and reduced reflected light can be obtained. When the conductive anti-reflection film is used, a cathode ray tube that is almost free from the AEF (Alternating Electric Field) and that displays a high quality picture for a long time can be obtained.

Abstract: Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.

Abstract: A process of growing silicon oxide to a highly calibrated thickness is provided. In one embodiment, a silicon precursor material is deposited to a first thickness on a substrate, such as a fused glass substrate used for forming microlithography masks. The precursor material is then selectively exposed to ionization and the non-ionized portions of the precursor material are then selectively etched leaving only the implanted portion of the precursor material of the first thickness. The implanted material is then oxidized resulting in an oxide structure having a thickness that is directly correlated to the initial thickness and the coefficient of oxidation. In one embodiment, a selective etch, such as TMAH, is used to remove unimplanted silicon which results in less than one percent etching of the implanted silicon.

Abstract: Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

Abstract: A CVD apparatus for processing semiconductor wafers (W) one by one has a process chamber (2) and a worktable (3). A resistance heating wire (31) is embedded in the worktable such that the upper surface of the worktable functions as a mount surface (3a) for mounting a wafer. The worktable is provided therein with first support means (4) having three vertical lifter pins (41, 42, 43) and second support means (5) having three vertical lifter pins (51, 52, 53). The wafer is moved down from a transfer position to the mount surface by the second support means. The wafer is heated on the mount surface up to a process temperature by contact heating, then is moved by the first support means up to a process position where it is slightly floated above the mount surface. The wafer is heated at the process position and kept at the process temperature by non-contact heating with radiation heat from the mount surface. In this state, a process gas is supplied and a polysilicon film is formed on the wafer.

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines.

Abstract: A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.

Abstract: A method is provided for eliminating the dishing effect of the chemical mechanical polishing (CMP) process on wide inlaid conductor leads in the layer of dielectric on a semiconductor device. A silicon dioxide dielectric having narrow and wide trenches is first coated with a blanket deposition of conductor material. The conductor material is coated with a photoresist and patterned with a reverse photo image of the trenches. The photoresist is etched leaving the photoresist over the trenches and the conductor material exposed between the trenches. The conductor material is etched removing the conductor material between the trenches and leaving the original thickness of conductor material over the trenches. The remaining photoresist is removed and the conductor material subject to CMP with the original thickness of conductor material acting to prevent dishing.

Abstract: The invention includes methods of forming a conductive silicide layers on silicon comprising substrates, and methods of forming conductive silicide contacts. In one implementation, a method of forming a conductive silicide layer on a silicon comprising substrate includes reacting oxygen with silicon of a silicon comprising substrate to form oxides of silicon from silicon of the substrate. The oxides of silicon include stoichiometric silicon dioxide and substoichiometric silicon dioxide. The stoichiometric silicon dioxide and substoichiometric silicon dioxide are exposed to ozone to transform at least some of the substoichiometric silicon dioxide to stoichiometric silicon dioxide. After the exposing, a conductive metal silicide is formed in electrical connection with silicon of the silicon comprising substrate.

Abstract: A method is provided for forming metal layers in semiconductor channels or vias by using a very high pressure ionized metal deposition technique which results in improved sidewall step coverage with enhanced subsequent filling of the channel or vias by conductive materials. To obtain the very high pressure in excess of 100 mT, the plasma coil power is increased and the gas flow is increased while maintaining a constant pumping feed in the ionized metal deposition equipment.

Abstract: In a process of forming a metal film, when metal wiring is formed on a diffusion layer (an electrode, etc.) of a circuit element formed on a silicon semiconductor wafer, a Ti film is deposited on a surface of a processed body by PECVD using TiCl.sub.4 gas and H.sub.2 gas as material gas. A Ti--Si--N film is formed on the diffusion layer surface by adding N.sub.2 gas to the material gas, and the Ti film is formed subsequently on the Ti--Si--N film. The Ti--Si--N film suppresses diffusion of silicon from the semiconductor wafer side.

Abstract: A method for fabricating a copper, or a copper-titanium nitride-titanium, interconnect structure, using a low temperature RIE patterning procedure, has been developed. The RIE patterning procedure features the use of SiCl.sub.4 and nitrogen, as reactants, with amount of nitrogen supplied, being equal to, or greater than, the SiCl.sub.4 level. The addition of nitrogen, to the etching ambient, results in the formation of a non-cross-linked, by-product, which is easily removed during the patterning procedure, this not interfering with the creation of interconnect structure. Without the addition of nitrogen, a cross-linked, by-product, would be formed, during the low temperature RIE procedure, with the redeposited, cross-linked, by-product, interfering with the patterning of the copper interconnect structure.

Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer.

Abstract: A process and structure are described wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first depositing the various layers needed by the gate pedestals in both the logic and the memory areas and then forming the two sets of gate pedestals in separate steps. Gates located in the logic area are formed only from polysilicon while those located in the memory areas also have an overlay of tungsten silicide topped by a hard mask of silicon nitride. With the two sets of gates in place, source/drain regions are formed in the usual way. This includes growing of silicon nitride spacers on the vertical sides of the pedestals. The pedestals in the memory area are much longer than those in the logic area since they extend all the way to the top of the hard masks.