Patents Examined by Robert Culbert
  • Patent number: 9997365
    Abstract: A method of manufacturing a semiconductor device includes: loading a substrate into a process container after dry-etching a portion of a silicon film formed in a recess on the substrate; performing etching to partially or entirely remove the silicon film remaining on a side wall inside the recess by supplying an etching gas selected from a hydrogen bromide gas and a hydrogen iodide gas into the process container of a vacuum atmosphere while heating the substrate; subsequently forming a silicon film inside the recess; and heating the substrate to increase a grain size of the silicon film.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 12, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 9991133
    Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 5, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Cheryl Pereira, Nihar Mohanty, Lior Huli
  • Patent number: 9991111
    Abstract: In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 5, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiro Ogawa, Tatsuhiko Koide, Shinsuke Kimura, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 9991179
    Abstract: Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a semiconductor device, including: (a) receiving a thickness information of a wiring layer formed on a substrate including: a first interlayer insulation film; and the wiring layer disposed on the first interlayer insulation film, the wiring layer including: copper-containing films used as wiring; and an inter-wiring insulation film having trenches filled with the copper-containing films and insulating the copper-containing films; (b) placing the substrate on a substrate support installed in a process chamber; and (c) etching the wiring layer using an etching gas based on an etching control value corresponding to the thickness information of the wiring layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 5, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naofumi Ohashi, Kazuyuki Toyoda, Satoshi Shimamoto, Toshiyuki Kikuchi
  • Patent number: 9984895
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; a dihydroxy bis-sulfide; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 29, 2018
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Lin-Chen Ho, Wei-Wen Tsai, Cheng-Ping Lee
  • Patent number: 9982351
    Abstract: An aluminum alloy article having improved surface contrast and an associated method are provided. The method includes grinding a surface of the article, diamond polishing the surface of the article, and removing ?-aluminum matrix material from the surface by fine polishing the surface with a suspension containing colloidal silica and a caustic substance, wherein the caustic substance has a higher pH value than the pH value of colloidal silica.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 29, 2018
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Adam P. Rabe
  • Patent number: 9960016
    Abstract: In a plasma processing method in which multiple cycles, each of which includes a first stage of generating plasma of a first processing gas containing a first gas and a second stage of generating plasma of a second processing gas containing the first gas and a second gas, are performed, a time difference between a start time point of a time period during which the second stage is performed and a start time point of an output of the second gas from a gas supply system is decided automatically according to a recipe. A delay time corresponding to flow rates of the first gas and the second gas in the second stage is specified from a function or a table. The output of the second gas is begun prior to the start time point of the second stage by a time difference set based on the delay time.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 1, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kumiko Ono, Hiroshi Tsujimoto, Koichi Nagami
  • Patent number: 9953862
    Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 24, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda
  • Patent number: 9953840
    Abstract: A substrate processing method according to the present disclosure includes: a liquid processing process of supplying a processing liquid to a substrate having a surface on which a pattern having a plurality of convex portions is formed; a drying process of removing the processing liquid existing on the surface of the substrate dry the substrate, and a separating process of separating a sticking portion between adjacent ones of the convex portions after the drying process.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: April 24, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Marumoto, Hisashi Kawano, Hiromi Kiyose, Mitsunori Nakamori, Kazuyuki Mitsuoka
  • Patent number: 9953912
    Abstract: Work pieces and methods of forming through holes in substrates are disclosed. In one embodiment, a method of forming a through hole in a substrate by drilling includes affixing an exit sacrificial cover layer to a laser beam exit surface of the substrate, positioning a laser beam in a predetermined location relative to the substrate and corresponding to a desired location for the through hole, and forming the through hole by repeatedly pulsing the laser beam into an entrance surface of the substrate and through a bulk of the substrate. The method further includes forming a hole in the exit sacrificial cover layer by repeatedly pulsing the laser beam into the through hole formed in the substrate such that the laser beam passes through the laser beam exit surface of the substrate and into the exit sacrificial cover layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 24, 2018
    Assignee: Corning Incorporated
    Inventor: Uta-Barbara Goers
  • Patent number: 9946159
    Abstract: A fragmentation pattern is formed on a surface of a warhead using a lithographic process. A photoresistant material is coated on an interior surface of the warhead casing. A portion of the photoresistant material is selectively cured by projecting an image of the fragmentation pattern onto the photoresistant material. The uncured portion of the photoresistant material is removed and an etchant is applied to the exposed portion of the warhead casing surface thereby etching the fragmentation pattern. Alternatively, a protective coating is applied over the entire surface thereby creating the fragmentation pattern.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 17, 2018
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Paul C. Manz, Philip J. Magnotti, Ductri H. Nguyen
  • Patent number: 9944828
    Abstract: The invention provides a chemical-mechanical polishing composition including (a) an abrasive comprising alumina particles, silica particles, or a combination thereof, (b) a rate accelerator comprising a phosphonic acid, an N-heterocyclic compound, or a combination thereof, (c) a corrosion inhibitor comprising an amphoteric surfactant, a sulfonate, a phosphonate, a carboxylate, a fatty acid amino acid, an amine, an amide, or a combination thereof, (d) an oxidizing agent, and (e) an aqueous carrier. The invention also provides a method of polishing a substrate, especially a substrate comprising a cobalt layer, with the polishing composition.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 17, 2018
    Assignee: Cabot Microelectronics Corporation
    Inventors: Elise Sikma, Witold Paw, Benjamin Petro, Jeffrey Cross, Glenn Whitener
  • Patent number: 9941123
    Abstract: A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SO2 or COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N2, H2, or NH3, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 10, 2018
    Assignee: Lam Research Corporation
    Inventors: Mirzafer Abatchev, Qian Fu, Yasushi Ishikawa
  • Patent number: 9938420
    Abstract: A method of manufacturing metallic articles from a metal substrate includes the steps of: a) jetting an image with a UV curable inkjet ink on at least one surface of the metallic substrate; b) UV curing the image; c) electroplating or acidic etching the at least one metallic surface not covered by the UV cured image; and d) stripping or solubilizing the UV cured image by an aqueous alkaline solution; wherein the UV curable inkjet ink has a viscosity of no more than 100 mPa·s at 25° C. and at a shear rate of 1,000 s?1; and wherein the UV curable inkjet ink contains a specific polymerizable composition and up to 20 wt % of photoinitiator including at least one of an acyl phosphine oxide photoinitiator and a thioxanthone photoinitiator.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 10, 2018
    Assignee: AGFA-GEVAERT
    Inventors: Rita Torfs, Roel De Mondt, Blanca Maria Pastor Ramirez, Johan Loccufier
  • Patent number: 9941131
    Abstract: A method for applying developer over a semiconductor wafer is provided. The method includes moving a nozzle over the center of the semiconductor wafer. The nozzle extends across the semiconductor wafer. The method also includes rotating the semiconductor wafer by a dispensing rotation angle that is less than 180 degrees. The method further includes dispensing developer over the semiconductor wafer relative to alignment marks formed on the semiconductor wafer while the semiconductor wafer is rotated by the dispensing rotation angle.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hung Lin, Hsiao-Yi Wang, Yen-Min Liao, Hsin-Jung Lu, Diau-Tang Huang
  • Patent number: 9941108
    Abstract: Plasma is generated using elemental hydrogen, a weak oxidizing agent, and a fluorine containing gas. An inert gas is introduced to the plasma downstream of the plasma source and upstream of a showerhead that directs gas mixture into the reaction chamber where the mixture reacts with the high-dose implant resist. The process removes both the crust and bulk resist layers at a high strip rate, and leaves the work piece surface substantially residue free with low silicon loss.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 10, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Haruhiro Harry Goto, David Cheung
  • Patent number: 9941121
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai
  • Patent number: 9935023
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya, Kentaro Yamada
  • Patent number: 9934945
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • Patent number: 9934987
    Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee